Jae-Seok Yang

According to our database, Jae-Seok Yang authored at least 13 papers between 2003 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs.

Krit Athikulwongse, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2012

Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper).

Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Design for manufacturability and reliability for TSV-based 3D ICs.

David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Chemical-mechanical polishing aware application-specific 3D NoC design.

Wooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Layout aware line-edge roughness modeling and poly optimization for leakage minimization.

Yongchan Ban, Jae-Seok Yang

Proceedings of the 48th Design Automation Conference, 2011

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs.

Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization.

Kun Yuan, Jae-Seok Yang, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Stress-driven 3D-IC placement with TSV keep-out zone and regularity study.

Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

TSV stress aware timing analysis with applications to 3D-IC layout optimization.

Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan

Proceedings of the 47th Design Automation Conference, 2010

A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography.

Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, David Z. Pan

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2008

Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner.

Jae-Seok Yang, Andrew R. Neureuther

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Overlay aware interconnect and timing variation modeling for double patterning technology.

Jae-Seok Yang, David Z. Pan

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2003

Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis.

Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003