Jae-Koo Park
According to our database1,
Jae-Koo Park
authored at least 6 papers
between 2013 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
A 80Gb/s/pin Single-Ended PAM-4 Transmitter With an Edge Boosting Auxiliary Driver and a 4-Tap FFE in 28-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2021
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3<sup>rd</sup>-Generation 10nm DRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2019
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.
IEEE J. Solid State Circuits, 2019
2018
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2013
Power-Efficient Fast Write and Hidden Refresh of ReRAM Using an ADC-Based Sense Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2013