Jae-Ick Son
According to our database1,
Jae-Ick Son
authored at least 5 papers
between 2016 and 2024.
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Collaborative distances:
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Bibliography
2024
13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2021
A 512Gb 3b/Cell 7<sup>th</sup> -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
4.1 A 39GHz-Band CMOS 16-Channel Phased-Array Transceiver IC with a Companion Dual-Stream IF Transceiver IC for 5G NR Base-Station Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2017
IEEE J. Solid State Circuits, 2017
2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016