Jacques-Olivier Klein
Orcid: 0000-0002-6923-5276
According to our database1,
Jacques-Olivier Klein
authored at least 85 papers
between 2002 and 2023.
Collaborative distances:
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Bibliography
2023
Improving Normalizing Flows with the Approximate Mass for Out-of-Distribution Detection.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
2021
Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation Per Synapse.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks.
CoRR, 2021
2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Microelectron. J., 2019
Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays.
CoRR, 2019
In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks.
CoRR, 2019
IEEE Access, 2019
Contrasting Advantages of Learning With Random Weights and Backpropagation in Non-Volatile Memory Neural Networks.
IEEE Access, 2019
Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
Multiscaled Simulation Methodology for Neuro-Inspired Circuits Demonstrated with an Organic Memristor.
IEEE Trans. Multi Scale Comput. Syst., 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Offset Analysis and Design Optimization of a Dynamic Sense Amplifier for Resistive Memories.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
2016
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Biomed. Circuits Syst., 2016
A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.
Microelectron. Reliab., 2016
J. Syst. Archit., 2016
Stochastic spintronic device based synapses and spiking neurons for neuromorphic computation.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
A novel circuit design of true random number generator using magnetic tunnel junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Exploiting the short-term to long-term plasticity transition in memristive nanodevice learning architectures.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
2015
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Spin-Transfer Torque Magnetic Memory as a Stochastic Memristive Synapse for Neuromorphic Systems.
IEEE Trans. Biomed. Circuits Syst., 2015
Microelectron. Reliab., 2015
ACM J. Emerg. Technol. Comput. Syst., 2015
On-Chip Universal Supervised Learning Methods for Neuro-Inspired Block of Memristive Nanodevices.
ACM J. Emerg. Technol. Comput. Syst., 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Supervised learning with organic memristor devices and prospects for neural crossbar arrays.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses.
Microelectron. Reliab., 2014
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.
J. Parallel Distributed Comput., 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014
Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A low-cost built-in error correction circuit design for STT-MRAM reliability improvement.
Microelectron. Reliab., 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Design study of efficient digital order-based STDP neuron implementations for extracting temporal features.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
2012
CoRR, 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Bioinspired networks with nanoscale memristive devices that combine the unsupervised and supervised learning approaches.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Microelectron. Reliab., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
2008
2007
IEEE Trans. Instrum. Meas., 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2005
Proceedings of the Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 2005
2004
An improved analog computation cell for Paris II, a programmable vision chip.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2002
Int. J. Circuit Theory Appl., 2002