Jacob Savir

According to our database, Jacob Savir authored at least 75 papers between 1980 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2006

Coefficient-based test of parametric faults in analog circuits.

Zhen Guo, Jacob Savir

IEEE Trans. Instrum. Meas., 2006

Effect of BIST Pretest on IC Defect Level.

Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2006

BIST Pretest of ICs: Risks and Benefits.

Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

2005

Built-in online and offline test of airborne digital systems.

Jacob Savir

IEEE Trans. Instrum. Meas., 2005

Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths.

Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2005

Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST.

Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2005

2004

Analog Circuit Test Using Transfer Function Coefficient Estimates.

Zhen Guo, Jacob Savir

IEICE Trans. Inf. Syst., 2004

Scan Latch Design for Test Applications.

Amit M. Sheth, Jacob Savir

J. Electron. Test., 2004

Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.

Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Single-clock, single-latch, scan design.

Amit M. Sheth, Jacob Savir

IEEE Trans. Instrum. Meas., 2003

Test limitations of parametric faults in analog circuits.

Jacob Savir, Zhen Guo

IEEE Trans. Instrum. Meas., 2003

Analog Circuit Test using Transfer Function Coe .cient Estimates.

Zhen Guo, Jacob Savir

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

On the Detectability of Parametric Faults in Analog Circuits.

Jacob Savir, Zhen Guo

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Observer-Based Test of Analog Linear Time-Invariant Circuits.

Zhen Guo, Jacob Savir

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

BIST Analysis of an Embedded Memory Associated Logic.

Jacob Savir

VLSI Design, 2001

Test Generators Need to be Modified to Handle CMOS Designs.

Jacob Savir

VLSI Design, 2001

BIST-Based Fault Diagnosis in the Presence of Embedded Memories.

Jacob Savir

VLSI Design, 2001

On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks.

Zhen Guo, Xi Min Zhang, Jacob Savir, Yun-Qing Shi

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Distributed BIST Architecture to Combat Delay Faults.

Jacob Savir

J. Electron. Test., 2000

On-line and off-line test of airborne digital systems: a reliability study.

Jacob Savir

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

MUST: multiple-stem analysis for identifying sequentially untestable faults.

Qiang Peng, Miron Abramovici, Jacob Savir

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

On testing safety-sensitive digital systems.

Jacob Savir

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Distributed Generation of Weighted Random Patterns.

Jacob Savir

IEEE Trans. Computers, 1999

Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections.

Jacob Savir

J. Electron. Test., 1999

Design for Testability to Combat Delay Faults.

Jacob Savir

Proceedings of the IEEE International Conference On Computer Design, 1999

Memory Chip BIST Architecture.

Jacob Savir

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998

Redundancy revisited.

Jacob Savir

IEEE Trans. Very Large Scale Integr. Syst., 1998

Random pattern testability of memory address logic.

Jacob Savir

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Salvaging Test Windows in BIST Diagnostics.

Jacob Savir

IEEE Trans. Computers, 1998

Random Pattern Testability of Memory Control Logic.

Jacob Savir

IEEE Trans. Computers, 1998

On-Chip Weighted Random Patterns.

Jacob Savir

J. Electron. Test., 1998

BIST Diagnostics, Part 1: Simulation Models.

Jacob Savir

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Reduced Latch Count Shift Registers.

Jacob Savir

J. Electron. Test., 1997

Module Level Weighted Random Patterns.

Jacob Savir

J. Electron. Test., 1997

Delay Test Generation: A Hardware Perspective.

Jacob Savir

J. Electron. Test., 1997

Salvaging test windows in BIST diagnostic.

Jacob Savir

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Scan Latch Design for Delay Test.

Jacob Savir

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers.

Jacob Savir

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

Reducing the MISR Size.

Jacob Savir

IEEE Trans. Computers, 1996

Delay Fault Testing: How Robust are Our Models?

Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1995

Shrinking wide compressors [BIST].

Jacob Savir

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

On shrinking wide compressors.

Jacob Savir

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Generator choices for delay test.

Jacob Savir

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

On broad-side delay test.

Jacob Savir, Srinivas Patil

IEEE Trans. Very Large Scale Integr. Syst., 1994

1993

Built-In Self-Test: Milestones and Challenges.

Jacob Savir, Paul H. Bardell

VLSI Design, 1993

Scan-based transition test.

Jacob Savir, Srinivas Patil

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992

A Multiple Seed Linear Feedback Shift Register.

Jacob Savir, William H. McAnney

IEEE Trans. Computers, 1992

Statistical Resistance to Detection.

A. Boneh, Jacob Savir

IEEE Trans. Computers, 1992

AC strength of a pattern generator.

Jacob Savir, Robert F. Berry

J. Electron. Test., 1992

Developments in delay testing.

Jacob Savir

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Skewed-Load Transition Test: Part 1, Calculus.

Jacob Savir

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Skewed-Load Transition Test: Part 2, Coverage.

Srinivas Patil, Jacob Savir

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

Partitioning of polynomial tasks: test generation, an example.

Jacob Savir, Paul H. Bardell

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Testing for Coupled Cells in Random-Access Memories.

Jacob Savir, William H. McAnney, Salvatore R. Vecchio

IEEE Trans. Computers, 1991

At-Speed Test is not Necessarily an AC Test.

Jacob Savir, Robert F. Berry

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

AC product defect level and yield loss.

Jacob Savir

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1988

Random Pattern Testability of Delay Faults.

Jacob Savir, William H. McAnney

IEEE Trans. Computers, 1988

Built-In Checking of the Correct Self-Test Signature.

William H. McAnney, Jacob Savir

IEEE Trans. Computers, 1988

Identification of Failing Tests with Cycling Registers.

Jacob Savir, William H. McAnney

Proceedings of the Proceedings International Test Conference 1988, 1988

Why Partial Design Verification Works Better Than It Should.

Jacob Savir

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

Fault Propagation Through Embedded Multiport Memories.

Jacob Savir, William H. McAnney, Salvatore R. Vecchio

IEEE Trans. Computers, 1987

1986

The Bidirectional Double Latch (BDDL).

Jacob Savir

IEEE Trans. Computers, 1986

1985

Layout Influences Testability.

Thomas H. Spencer, Jacob Savir

IEEE Trans. Computers, 1985

Random Pattern Testing for Address-Line Faults in an Embedded Multiport Memory.

Jacob Savir, William H. McAnney, Salvatore R. Vecchio

Proceedings of the Proceedings International Test Conference 1985, 1985

Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory.

Jacob Savir, William H. McAnney, Salvatore R. Vecchio

Proceedings of the Proceedings International Test Conference 1985, 1985

1984

Random Pattern Testability.

Jacob Savir, Gary S. Ditlow, Paul H. Bardell

IEEE Trans. Computers, 1984

On Random Pattern Test Length.

Jacob Savir, Paul H. Bardell

IEEE Trans. Computers, 1984

1983

Good Controllability and Observability Do Not Guarantee Good Testability.

Jacob Savir

IEEE Trans. Computers, 1983

A New Empirical Test for the Quality of Random Integer Generators.

Jacob Savir

IEEE Trans. Computers, 1983

1981

Syndrome-Testing of "Syndrome-Untestable" Combinational Circuits.

Jacob Savir

IEEE Trans. Computers, 1981

The Weighted Syndrome Sums Approach to VLSI Testing.

Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith

IEEE Trans. Computers, 1981

VLSI Self-Testing Based on Syndrome Techniques.

Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith

Proceedings of the Proceedings International Test Conference 1981, 1981

1980

Detection of Single Intermittent Faults in Sequential Circuits.

Jacob Savir

IEEE Trans. Computers, 1980

Syndrome-Testable Design of Combinational Circuits.

Jacob Savir

IEEE Trans. Computers, 1980

Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection.

Jacob Savir

IEEE Trans. Computers, 1980