Jacob Botimer

Orcid: 0000-0003-0670-7405

According to our database1, Jacob Botimer authored at least 6 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration.
IEEE J. Solid State Circuits, April, 2024

2023
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm<sup>2</sup> AIB 2.0 Interface to Provide Versatile Workload Acceleration.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2021
A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
A 1.87-mm<sup>2</sup> 56.9-GOPS Accelerator for Solving Partial Differential Equations.
IEEE J. Solid State Circuits, 2020

2019
CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

An Sram-Based Accelerator for Solving Partial Differential Equations.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019


  Loading...