Jack S. N. Jean

According to our database, Jack S. N. Jean authored at least 22 papers between 1990 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Architecture and operating system support for two-dimensional runtime partial reconfiguration.

Fei Wang, Jack S. N. Jean

J. Supercomput., 2012

2010

Parameterized AND-OR Trees for FPGA Design Space Exploration.

Srikanth Nadella, Andrew Dittes, Jack S. N. Jean

Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

2006

Architectural Support for Runtime 2D Partial Reconfiguration.

Fei Wang, Jack S. N. Jean

Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

2005

Aspect Ratio Effects on Reconfigurable Computing.

Fei Wang, Jack S. N. Jean, Shuxia Sun

Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

2004

Design Enumeration of Mapping 2D FFT onto FPGA Based Reconfigurable Computers.

Xinzhong Guo, Jack S. N. Jean

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2003

Mapping of generalized template matching onto reconfigurable computers.

Xuejun Liang, Jack S. N. Jean

IEEE Trans. Very Large Scale Integr. Syst., 2003

A Study of Mapping Generalized Sliding Window Operations on Reconfigurable Computers.

Jack S. N. Jean, Xinzhong Guo, Fei Wang, Lei Song, Ying Zhang

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

2001

Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems.

Xuejun Liang, Jack S. N. Jean, Karen A. Tomko

J. Supercomput., 2001

2000

Automatic Target Recognition with Dynamic Reconfiguration.

Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko, Yan Wang

J. VLSI Signal Process., 2000

Interface Design for the Mapping of Generalized Template Matching on Reconfigurable Systems.

Xuejun Liang, Jack S. N. Jean

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

1999

Concurrency Preserving Partitioning Algorithm for Parallel Logic Simulation.

Hong K. Kim, Jack S. N. Jean

VLSI Design, 1999

Processor array design with FPGA area constraint.

Joseph A. Fernando, Jack S. N. Jean

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Dynamic Reconfiguration to Support Concurrent Applications.

Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Jignesh Shah, Robert Cook

IEEE Trans. Computers, 1999

Accelerating an IR Automatic Target Recognition Application with FPGAs.

Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko

Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998

Parallel Optimistic Logic Simulation with Event Lookahead.

Hong K. Kim, Jack S. N. Jean

Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998

1996

Concurrency Preserving Rartitioning (CPP) for Parallel Logic Simulation.

Hong K. Kim, Jack S. N. Jean

Proceedings of the Tenth Workshop on Parallel and Distributed Simulation, 1996

1995

Interfacing FPGA/VLSI Processor Arrays.

Joseph A. Fernando, Jack S. N. Jean

Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994

Weight smoothing to improve network generalization.

Jack S. N. Jean, Jin Wang

IEEE Trans. Neural Networks, 1994

Segmentation of merged characters by neural networks and shortest path.

Jin Wang, Jack S. N. Jean

Pattern Recognit., 1994

1993

Resolving multifont character confusion with neural networks.

Jin Wang, Jack S. N. Jean

Pattern Recognit., 1993

1990

A new distance measure for binary images.

Jack S. N. Jean

Proceedings of the 1990 International Conference on Acoustics, 1990

Fault-tolerant array processors using N-and-half-track switches.

Jack S. N. Jean

Proceedings of the Application Specific Array Processors, 1990