Jabulani Nyathi

According to our database, Jabulani Nyathi authored at least 17 papers between 1996 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

An experimental justification for the proportionality between the coherence bandwidth and the root mean square time delay spread using deterministic time of arrivals.

Saqer Alhloul, Uri Rogers, Donald C. Richter, Jabulani Nyathi

Phys. Commun., 2021

2017

Slowing the none-critical path to improve carry look-ahead adder power dissipation.

Jabulani Nyathi, Abubaker Mutumba

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2007

Serial Addition: Locally Connected Architectures.

Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Walid Ibrahim

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Multiple clock domain synchronization for network on chip architectures.

Jabulani Nyathi, Souradip Sarkar, Partha Pratim Pande

Proceedings of the 2007 IEEE International SOC Conference, 2007

Evaluation of CPU Utilization Under a Hardware-software Partitioned Enviroment (Migrating Software to Hardware).

Hsiang-Ling Jamie Lin, Jabulani Nyathi, Clint Cole

Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007

2006

Logic circuits operating in subthreshold voltages.

Jabulani Nyathi, Brent Bero

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

An Efficient Key Update Scheme For Wireless Sensor Networks.

Kamini Prajapati, Jabulani Nyathi

Proceedings of the 2006 International Conference on Wireless Networks, 2006

Femto Joule Switching for Nano Electronics.

Valeriu Beiu, Jabulani Nyathi, Snorre Aunet, Mawahib H. Sulieman

Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

2005

Decoupled dynamic ternary content addressable memories.

José G. Delgado-Frias, Jabulani Nyathi, Suryanarayana Tatapudi

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A distributed FIFO scheme for on chip communication.

Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

On the Advantages of Serial Architectures for Low-Power Reliable Computations.

Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

A Distributed FIFO Scheme for System on Chip Inter-Component Communication.

Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias

Proceedings of the International Conference on Embedded Systems and Applications, 2004

A High Performance, Low Area Overhead Carry Lookahead Adder.

James Levy, Jabulani Nyathi

Proceedings of the International Conference on Embedded Systems and Applications, 2004

2000

A wave-pipelined CMOS associate router for communication switches.

José G. Delgado-Frias, Jabulani Nyathi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A wave-pipelined router architecture using ternary associative memory.

José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1998

A VLSI High-Performance Encoder with Priority Lookahead.

José G. Delgado-Frias, Jabulani Nyathi

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1996

A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh.

José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996