Ja-Yol Lee
Orcid: 0000-0001-8834-8527
According to our database1,
Ja-Yol Lee
authored at least 8 papers
between 2006 and 2022.
Collaborative distances:
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Bibliography
2022
A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications.
IEEE Access, 2022
2021
A Ka-Band FMCW PLL Synthesizer with 8.5-GHz Bandwidth for High-Precision High-Resolution Sub-mmWave Radar Sensing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Untrimmed BGR of 1.1% $3\sigma$ Based on Dynamic-Biased Op Amp With Reduced ${V} _{\rm off}$.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
2015
410-GHz CMOS imager using a 4<sup>th</sup> sub-harmonic mixer with effective NEP of 0.3 fW/Hz<sup>0.5</sup> at 1-kHz noise bandwidth.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
A 230ns settling time type-I PLL with 0.96mW TDC power and simple TV calculation algorithm.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
2011
A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006