J. W. Maes

According to our database1, J. W. Maes authored at least 5 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

2006
2008
2010
2012
2014
2016
2018
2020
2022
2024
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Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

DRAM-Peri FinFET - A Thermally-Stable High-Performance Advanced CMOS RMG Platform with Mo-Based pWFM for sub-10nm DRAM.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Pure-Metal Replacement Gate for Reliable 30 nm Pitch Scaled 3D NAND Flash.
Proceedings of the IEEE International Memory Workshop, 2024

2023
Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2005
Potential remedies for the V<sub>T</sub>/V<sub>fb</sub>-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey.
Microelectron. Reliab., 2005


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