J. W. Maes
According to our database1,
J. W. Maes
authored at least 5 papers
between 2005 and 2024.
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Collaborative distances:
Timeline
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2024
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2024
Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
DRAM-Peri FinFET - A Thermally-Stable High-Performance Advanced CMOS RMG Platform with Mo-Based pWFM for sub-10nm DRAM.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Proceedings of the IEEE International Memory Workshop, 2024
2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2005
Potential remedies for the V<sub>T</sub>/V<sub>fb</sub>-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey.
Microelectron. Reliab., 2005