J. V. R. Ravindra

According to our database, J. V. R. Ravindra authored at least 27 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Exploring Deep Learning Models for Accurate Alzheimer's Disease Classification based on MRI Imaging.

Irfan Sadiq Rahat, Tuhin Hossain, Hritwik Ghosh, Kamjula Lakshmi Kanth Reddy, Srinivas Kumar Palvadi, J. V. R. Ravindra

EAI Endorsed Trans. Pervasive Health Technol., 2024

Convolutional Neural Networks in Malaria Diagnosis: A Study on Cell Image Classification.

Hritwik Ghosh, Irfan Sadiq Rahat, J. V. R. Ravindra, Balajee J, Mohammad Aman Ullah Khan, J. Somasekar

EAI Endorsed Trans. Pervasive Health Technol., 2024

Exploring Deep Learning Models for Accurate Alzheimer's Disease Classification based on MRI Imaging.

Hritwik Ghosh, Pavan Kumar P, Irfan Sadiq Rahat, Md Mehedi Hasan Nipu, Garigipati Rama Krishna, J. V. R. Ravindra

EAI Endorsed Trans. Pervasive Health Technol., 2024

A Multi-Model Machine Learning Approach for Monitoring Calories Being Burnt During Workouts Using Smart Calorie Tracer.

Yagnesh Challagundla, Badri Narayanan K, Krishna Sai Devatha, Bharathi V. C, J. V. R. Ravindra

EAI Endorsed Trans. Pervasive Health Technol., 2024

Deep Learning-Driven Surveillance for Intrusion Identification using Proactive Intelligent Video Recognition.

Yagnesh Challagundla, Shreeya Dheera Parvatham, Sachi Nandan Mohanty, J. V. R. Ravindra

Proceedings of the IEEE International Conference on Advanced Video and Signal Based Surveillance, 2024

2023

Correction to: Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique.

B. Srikanth, J. V. R. Ravindra, P. Ramakrishna, D. Ajitha

Wirel. Pers. Commun., 2023

Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique.

B. Srikanth, J. V. R. Ravindra, P. Ramakrishna, D. Ajitha

Wirel. Pers. Commun., 2023

2022

Proffering Secure Energy Aware Network-On-Chip (Noc) Using Incremental Cryptogine.

Sangeeta Singh, J. V. R. Ravindra, B. Rajendra Naik

Sustain. Comput. Informatics Syst., 2022

2021

Accuracy evaluation of a trained neural network by energy efficient approximate 4: 2 compressor.

Lavanya Maddisetti, Ranjan K. Senapati, J. V. R. Ravindra

Comput. Electr. Eng., 2021

2020

The enhancement of security measures in advanced encryption standard using double precision floating point multiplication model.

B. Srikanth, M. Siva Kumar, J. V. R. Ravindra, K. Hari Kishore

Trans. Emerg. Telecommun. Technol., 2020

2019

Machine Learning Based Power Efficient Approximate 4: 2 Compressors for Imprecise Multipliers.

Lavanya Maddisetti, J. V. R. Ravindra

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Low-Power. High-Speed Adversarial Attack based 4: 2 Compressor as Full Adder for Multipliers in FIR Digital Filters.

Lavanya Maddisetti, J. V. R. Ravindra

Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

2018

Performance Metrics of Inexact Multipliers Based on Approximate 5: 2 Compressors.

Lavanya Maddisetti, J. V. R. Ravindra

Proceedings of the International SoC Design Conference, 2018

Performance Metrics of Imprecise Multipliers Based on Proximate Compressors for IIR Filters.

M. Lavanya, J. V. R. Ravindra

Proceedings of the 30th International Conference on Microelectronics, 2018

2016

Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip.

Sangeeta Singh, J. V. R. Ravindra, B. Rajendra Naik

Proceedings of the International SoC Design Conference, 2016

A novel and efficient design of golay encoder for ultra deep submicron technologies.

Chiranjeevi Sheelam, J. V. R. Ravindra

Proceedings of the 2016 International Conference on Advances in Computing, 2016

2013

A Novel Analytical Model for Analysis of Delay and Crosstalk in Non Linear RLC Interconnects for Ultra Low Power Applications.

J. V. R. Ravindra, Pandurangaiah Yagateela, L. V. Narasimha Prasad

Proceedings of the 15th International Conference on Computer Modelling and Simulation, 2013

Design of Ultra Lowpower Full Adder Using Modified Branch Based Logic Style.

Gangadhar Reddy Ramireddy, J. V. R. Ravindra, Harikrishna Kamatham

Proceedings of the Seventh UKSim/AMSS European Modelling Symposium, 2013

Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology.

Narasimha Rao Konijeti, J. V. R. Ravindra, Pandurangaiah Yagateela

Proceedings of the Seventh UKSim/AMSS European Modelling Symposium, 2013

2008

Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits.

J. V. R. Ravindra, M. B. Srinivas

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Delay and Energy Efficient Coding Techniques for Capacitive Interconnects.

J. V. R. Ravindra, M. B. Srinivas

J. Circuits Syst. Comput., 2007

Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach.

J. V. R. Ravindra, Srinivas Bala Mandalika

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs.

J. V. R. Ravindra, M. B. Srinivas

Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects.

J. V. R. Ravindra, M. B. Srinivas

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.

K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method.

K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005

A novel deep submicron low power bus coding technique.

K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas

Proceedings of the Third IASTED International Conference on Circuits, 2005