J. Th. van der Linden

According to our database, J. Th. van der Linden authored at least 12 papers between 1993 and 2002.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2002

Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume.

M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2000

Test point insertion for compact test sets.

M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999

Testability of the Philips 80C51 micro-controller.

M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Illegal State Space Identification for Sequential Circuit Test Generation.

M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the 1999 Design, 1999

1998

Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection.

J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Sequential Test Generation with Advanced Illegal State Search.

M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996

Accelerated Compact Test Set Generation for Three-State Circuits.

M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors.

J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Compact test sets for industrial circuits.

M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

1994

Test generation and three-state elements, buses, and bidirectionals.

J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/O.

J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993

Test Pattern Generation with Restrictors.

M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993