J. Rubén Titos Gil

Microprocess. Microsystems, 2024

2022

DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2022

Analysing software prefetching opportunities in hardware transactional memory.

[BibT_eX]

[DOI]

Marina Shimchenko

J. Supercomput., 2022

Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory.

[BibT_eX]

[DOI]

Víctor Nicolás-Conesa

Eduardo José Gómez-Hernández

Proceedings of the 30th Euromicro International Conference on Parallel, 2022

2021

Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations.

[BibT_eX]

[DOI]

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020

Concurrent Irrevocability in Best-Effort Hardware Transactional Memory.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2020

PfTouch: Concurrent page-fault handling for Intel restricted transactional memory.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2020

2019

Way Combination for an Adaptive and Scalable Coherence Directory.

[BibT_eX]

[DOI]

Antonio Flores

IEEE Trans. Parallel Distributed Syst., 2019

2017

Way-combining directory: an adaptive and scalable low-cost coherence directory.

[BibT_eX]

[DOI]

Antonio Flores

Santhosh Kumar Rethinagiri

Proceedings of the International Conference on Supercomputing, 2017

2016

Architectural support for efficient message passing on shared memory multi-cores.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2016

Energy minimization at all layers of the data center: The ParaDIME project.

[BibT_eX]

[DOI]

Oscar Palomar

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Hardware Approaches to Transactional Memory in Chip Multiprocessors.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Proceedings of the Handbook on Data Centers, 2015

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

Enhancing Garbage Collection Synchronization Using Explicit Bit Barriers.

[BibT_eX]

[DOI]

Jochen Hollmann

Per Stenström

Proceedings of the 44th International Conference on Parallel Processing, 2015

DiMP: Architectural Support for Direct Message Passing on Shared Memory Multi-cores.

[BibT_eX]

[DOI]

Proceedings of the 44th International Conference on Parallel Processing, 2015

2014

ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2014

Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems.

[BibT_eX]

[DOI]

J. Supercomput., 2014

Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

2013

Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2013

Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory.

[BibT_eX]

[DOI]

José M. García

IEEE Trans. Parallel Distributed Syst., 2013

SCIN-cache: Fast speculative versioning in multithreaded cores.

[BibT_eX]

[DOI]

Anurag Negi

ACM Trans. Archit. Code Optim., 2013

Techniques to improve performance in requester-wins hardware transactional memory.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

On the design of energy-efficient hardware transactional memory systems.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2013

2012

Hardware transactional memory with software-defined conflicts.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2012

Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the 20th Euromicro International Conference on Parallel, 2012

π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011

The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

ZEBRA: a data-centric, hybrid-policy hardware transactional memory design.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Processing, 2011

Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

Characterizing Energy Consumption in Hardware Transactional Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

2009

Speculation-based conflict resolution in hardware transactional memory.

[BibT_eX]

[DOI]

José Manuel García Carrasco

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2008

Characterization of Conflicts in Log-Based Transactional Memory (LogTM).

[BibT_eX]

[DOI]

José Manuel García Carrasco

Proceedings of the 16th Euromicro International Conference on Parallel, 2008

Directory-Based Conflict Detection in Hardware Transactional Memory.

[BibT_eX]

[DOI]