J. Joshua Yang
Orcid: 0000-0001-8242-7531Affiliations:
- University of Massachusetts, Department of Electrical and Computer Engineering, Amherst, MA, USA
According to our database1,
J. Joshua Yang
authored at least 42 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2024
Capacitor-Free Scalable CMOS Neuron Circuit With Compact Design and Low Power Consumption.
IEEE Access, 2024
2023
Parallel synaptic design of ferroelectric tunnel junctions for neuromorphic computing.
Neuromorph. Comput. Eng., June, 2023
Neuromorph. Comput. Eng., March, 2023
Early Prevention of Heart Attacks Using Memristor-Based Machine Learning and Surface Enhanced Raman Spectroscopy with Collapsible Nanofinger.
Proceedings of the IEEE International Conference on Metrology for eXtended Reality, 2023
2022
Neuromorph. Comput. Eng., 2022
2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2019
Nat. Mach. Intell., 2019
Nat. Mach. Intell., 2019
IEEE Des. Test, 2019
Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization.
CoRR, 2019
2018
Memristor-CMOS Analog Coprocessor for Acceleration of High-Performance Computing Applications.
ACM J. Emerg. Technol. Comput. Syst., 2018
Memristor Crossbars with 4.5 Terabits-per-Inch-Square Density and Two Nanometer Dimension.
CoRR, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
An energy-efficient and high-throughput bitwise CNN on sneak-path-free digital ReRAM crossbar.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
A closed-loop design to enhance weight stability of memristor based neural network chips.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
2016
Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Cyclical sensing integrate-and-fire circuit for memristor array based neuromorphic computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014
2013
ACM J. Emerg. Technol. Comput. Syst., 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
2010
Nat., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010