J. H. Lou

According to our database, J. H. Lou authored at least 5 papers between 1994 and 1998.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

1998

1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder.

J. H. Lou, James B. Kuo

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1997

A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI.

J. H. Lou, James B. Kuo

IEEE J. Solid State Circuits, 1997

1995

A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit.

James B. Kuo, K. W. Su, J. H. Lou

IEEE J. Solid State Circuits, August, 1995

A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable for VLSI using low-voltage BiCMOS technology.

James B. Kuo, K. W. Su, J. H. Lou, S. S. Chen, C. S. Chiang

IEEE J. Solid State Circuits, January, 1995

1994

A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit.

James B. Kuo, K. W. Su, J. H. Lou

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994