J. Gregory Steffan

Affiliations:
  • University of Toronto, Canada


According to our database1, J. Gregory Steffan authored at least 57 papers between 1998 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
Reducing the Performance Gap between Soft Scalar CPUs and Custom Hardware with TILT.
ACM Trans. Reconfigurable Technol. Syst., 2017

2014
Composing Multi-Ported Memories on FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2014

DART: A Programmable Architecture for NoC Simulation on FPGAs.
IEEE Trans. Computers, 2014

Virtualized Reconfigurable Hardware Resources in the SAVI Testbed.
Proceedings of the Testbeds and Research Infrastructure: Development of Networks and Communities, 2014

Comparing performance, productivity and scalability of the TILT overlay processor to OpenCL HLS.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Approaching overhead-free execution on FPGA soft-processors.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Producing high-quality real-time HDR video system with FPGA (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Speeding Up FPGA Placement: Parallel Algorithms and Methods.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013
Maximizing speed and density of tiled FPGA overlays via partitioning.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

TILT: A multithreaded VLIW soft processor family.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A Multithreaded VLIW Soft Processor Family.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
Portable, Flexible, and Scalable Soft Vector Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Caliper: Precise and Responsive Traffic Generator.
Proceedings of the IEEE 20th Annual Symposium on High-Performance Interconnects, 2012

OCTAVO: an FPGA-centric processor family.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Multi-ported memories for FPGAs via XOR.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Compiler Support for Fine-Grain Software-Only Checkpointing.
Proceedings of the Compiler Construction - 21st International Conference, 2012

11th Compiler-Driven Performance Workshop.
Proceedings of the Center for Advanced Studies on Collaborative Research, 2012

2011
Application-specific signatures for transactional memory in soft processors.
ACM Trans. Reconfigurable Technol. Syst., 2011

The Potential for a GPU-Like Overlay Architecture for FPGAs.
Int. J. Reconfigurable Comput., 2011

Understanding bloom filter intersection for lazy address-set disambiguation.
Proceedings of the SPAA 2011: Proceedings of the 23rd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2011

DART: A programmable architecture for NoC simulation on FPGAs.
Proceedings of the NOCS 2011, 2011

NetTM: faster and easier synchronization for soft multicores via transactional memory.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Programmer-assisted automatic parallelization.
Proceedings of the Center for Advanced Studies on Collaborative Research, 2011

2010
Caliper: a tool to generate precise and closed-loop traffic.
Proceedings of the ACM SIGCOMM 2010 Conference on Applications, 2010

A GPU-inspired soft processor for high-throughput acceleration.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Parallelizing FPGA placement using Transactional Memory.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Efficient multi-ported memories for FPGAs.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

9th Workshop on Compiler-Driven Performance.
Proceedings of the 2010 conference of the Centre for Advanced Studies on Collaborative Research, 2010

The case for hardware transactional memory in software packet processing.
Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

2009
Data parallel FPGA workloads: Software versus hardware.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Fast critical sections via thread scheduling for FPGA-based multithreaded processors.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Fine-grain performance scaling of soft vector processors.
Proceedings of the 2009 International Conference on Compilers, 2009

2008
Incrementally parallelizing database transactions with thread-level speculation.
ACM Trans. Comput. Syst., 2008

Compiler and hardware support for reducing the synchronization of speculative threads.
ACM Trans. Archit. Code Optim., 2008

Scaling Soft Processor Systems.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

VESPA: portable, scalable, and flexible FPGA-based vector processors.
Proceedings of the 2008 International Conference on Compilers, 2008

The potential for variable-granularity access tracking for optimistic parallelism.
Proceedings of the 2008 ACM SIGPLAN workshop on Memory Systems Performance and Correctness: held in conjunction with the Thirteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '08), 2008

2007
CMP Support for Large and Dependent Speculative Threads.
IEEE Trans. Parallel Distributed Syst., 2007

Exploration and Customization of FPGA-Based Soft Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Custom code generation for soft processors.
SIGARCH Comput. Archit. News, 2007

Improving Pipelined Soft Processors with Multithreading.
Proceedings of the FPL 2007, 2007

JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
Tolerating Dependences Between Large Speculative Threads Via Sub-Threads.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Improving cache locality for thread-level speculation.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Application-specific customization of soft processor microarchitecture.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

A probabilistic pointer analysis for speculative optimizations.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005
The STAMPede approach to thread-level speculation.
ACM Trans. Comput. Syst., 2005

Optimistic Intra-Transaction Parallelism on Chip Multiprocessors.
Proceedings of the 31st International Conference on Very Large Data Bases, Trondheim, Norway, August 30, 2005

The microarchitecture of FPGA-based soft processors.
Proceedings of the 2005 International Conference on Compilers, 2005

2004
Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads.
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004

2002
Improving Value Communication for Thread-Level Speculation.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Compiler optimization of scalar value communication between speculative threads.
Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), 2002

2000
A scalable approach to thread-level speculation.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

1998
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization.
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998


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