J.-F. de Marneffe

According to our database, J.-F. de Marneffe authored at least 2 papers between 2021 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions.

Jacopo Franco, Hiroaki Arimura, J.-F. de Marneffe, S. Brus, Romain Ritzenthaler, E. Dentoni Litta, Kris Croes, Ben Kaczer, N. Horiguchi

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2021

Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper.

Jacopo Franco, Hiroaki Arimura, J.-F. de Marneffe, A. Vandooren, L.-Å. Ragnarsson, Zhicheng Wu, Dieter Claes, E. Dentoni Litta, N. Horiguchi, Kris Croes, Dimitri Linten, Tibor Grasser, Ben Kaczer

Proceedings of the International Conference on IC Design and Technology, 2021