J. Balachandran

According to our database1, J. Balachandran authored at least 6 papers between 2005 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2006
Wafer-level package interconnect options.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Constant impedance scaling paradigm for interconnect synthesis.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Efficient Link Architecture for On-Chip Serial links and Networks.
Proceedings of the International Symposium on System-on-Chip, 2006

Constant Impedance Scaling Paradigm for Scaling LC transmission lines.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Analysis and modeling of power grid transmission lines.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Package level interconnect options.
Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005


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