J. B. Kuo

According to our database, J. B. Kuo authored at least 5 papers between 2002 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2008

Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application.

B. Chung, J. B. Kuo

Integr., 2008

2006

Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique.

B. Chung, J. B. Kuo

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology.

B. Chung, J. B. Kuo

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications.

G. Y. Liu, N. C. Wang, J. B. Kuo

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2002

0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems.

E. Shen, J. B. Kuo

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002