Iyad Ouaiss

According to our database, Iyad Ouaiss authored at least 16 papers between 1998 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Toward an Improvement of Engineering Teaming Skills Through an In-House Professionalism Course.

Mohammad Al-Abbas, Wissam Fawaz, Raymond Ghajar, Chadi Abou-Rjeily, Iyad Ouaiss, Zahi Nakad, George E. Nasr, Samer S. Saab

IEEE Trans. Educ., 2020

2015

Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations.

Grace Zgheib, Iyad Ouaiss

J. Circuits Syst. Comput., 2015

2011

Priority-Driven Area Optimization in High-Level Synthesis.

Maria Abi Saad, Iyad Ouaiss

J. Circuits Syst. Comput., 2011

A Novel Register-Binding Approach to Reduce Spurious Switching Activity in High-Level Synthesis.

Elie Elaaraj, Iyad Ouaiss

J. Circuits Syst. Comput., 2011

2010

A novel pseudorandom noise and band jammer generator using a composite sinusoidal function.

Samer S. Saab, Jad G. Hobeika, Iyad Ouaiss

IEEE Trans. Signal Process., 2010

Deadline-based connection setup in wavelength-routed WDM networks.

Wissam Fawaz, Iyad Ouaiss, Ken Chen, Harry G. Perros

Comput. Networks, 2010

2005

Optimizing register binding in FPGAs using simulated annealing.

Annie Avakian, Iyad Ouaiss

Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

2004

Storage Allocation for Diverse FPGA Memory Specifications.

Dalia Dagher, Iyad Ouaiss

Proceedings of the Field Programmable Logic and Application, 2004

Register Binding for FPGAs with Embedded Memory.

Hassan Al Atat, Iyad Ouaiss

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2001

Global memory mapping for FPGA-based reconfigurable systems.

Iyad Ouaiss, Ranga Vemuri

Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Memory Synthesis for FPGA-Based Reconfigurable Computers.

Amit Kasat, Iyad Ouaiss, Ranga Vemuri

Proceedings of the Field-Programmable Logic and Applications, 2001

Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers.

Iyad Ouaiss, Ranga Vemuri

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Efficient Resource Arbitration in Reconfigurable Computing Environments.

Iyad Ouaiss, Ranga Vemuri

Proceedings of the 2000 Design, 2000

1999

An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications.

Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss

Proceedings of the 36th Conference on Design Automation, 1999

1998

An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures.

Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri

Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

An Effective Design System for Dynamically Reconfigurable Architectures.

Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998