Ivo Bolsens

According to our database1, Ivo Bolsens authored at least 64 papers between 1985 and 2023.

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Bibliography

2023
Bridging Divides: Unifying AI Architectures from from Edge to Cloud.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

2020
Scalable System and Silicon Architectures to Handle the Workloads of the Post-Moore Era.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

2017
Pushing the boundaries of Moore's Law to transition from FPGA to All Programmable Platform.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

"All programmable FPGA, providing hardware efficiency to software programmers".
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2014
"All Programmable SOC FPGA for networking and computing in big data infrastructure".
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2010
Programming customized parallel architectures in FPGA.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

FPGA platforms leading the way in the application of 'more than Moore's' technology.
Proceedings of the International Conference on Field-Programmable Technology, 2010

2009
NoCs: It is about the memory and the programming model.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

2008
FPGA: The future platform for transforming, transporting and computing data.
Proceedings of the FPL 2008, 2008

2005
Plenary lecture [Second page is blank].
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Are we ready for system-level synthesis?
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
What happened to ASIC?: Go (recon)figure?
Proceedings of the 41th Design Automation Conference, 2004

2003
A scalable MPEG-4 wavelet-based visual texture compression system with optimized memory organization.
IEEE Trans. Circuits Syst. Video Technol., 2003

Challenges and Opportunities for FPGA Programmable System Platforms.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Panel Title: Reconfigurable Computing - Different Perspectives.
Proceedings of the 2003 Design, 2003

Fast, cheap and under control: the next implementation fabric.
Proceedings of the 40th Design Automation Conference, 2003

2002
Challenges and Opportunities for FPGA Platforms.
Proceedings of the Field-Programmable Logic and Applications, 2002

Reconfigurable SoC - What Will it Look Like?
Proceedings of the 2002 Design, 2002

Design Technology for Networked Reconfigurable FPGA Platforms.
Proceedings of the 2002 Design, 2002

2001
Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors.
J. VLSI Signal Process., 2001

80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital OFDM transceiver ASICs for wireless local area networks in the 5-GHz band.
IEEE J. Solid State Circuits, 2001

Efficient bit-error-rate estimation of multicarrier transceivers.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

High-level simulation of substrate noise generation from large digital circuits with multiple supplies.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Hardware/software partitioning of embedded system in OCAPI-xl.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
Chip-package codesign of a low-power 5-GHz RF front end.
Proc. IEEE, 2000

Analysis and experimental verification of digital substrate noise generation for epi-type substrates.
IEEE J. Solid State Circuits, 2000

Cost-Efficient C-Level Design of an MPEG-4 Video Decoder.
Proceedings of the Integrated Circuit Design, 2000

Compact Modeling of Nonlinear Distortion in Analog Communication Circuits.
Proceedings of the 2000 Design, 2000

A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers.
Proceedings of the 37th Conference on Design Automation, 2000

High-level simulation of substrate noise generation including power supply noise coupling.
Proceedings of the 37th Conference on Design Automation, 2000

1999
A Scalable Architecture for MPEG-4 Wavelet Quantization.
J. VLSI Signal Process., 1999

Optimal memory organization for scalable texture codecs in MPEG-4.
IEEE Trans. Circuits Syst. Video Technol., 1999

Implementation driven selection of wavelet filters for still image coding based on bitrange expansion.
Proceedings of the Third IEEE Workshop on Multimedia Signal Processing, 1999

High-level simulation and power modelling of mixed-signal front-ends for digital telecommunications.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

BANDIT: embedding analog-to-digital converters on digital telecom ASICs.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A Single-Package Solution for Wireless Transceivers.
Proceedings of the 1999 Design, 1999

A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement.
Proceedings of the 1999 Design, 1999

Single Chip or Hybrid System Integration.
Proceedings of the 1999 Design, 1999

Hardware Reuse at the Behavioral Level.
Proceedings of the 36th Conference on Design Automation, 1999

Implementation of a Scalable MPEG-4 Wavelet-Based Visual Texture Compression System.
Proceedings of the 36th Conference on Design Automation, 1999

A scalable architecture for MPEG-4 embedded zero tree coding.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
Low Power Digital Frequency Conversion Architectures.
J. VLSI Signal Process., 1998

A Technique for Combined Virtual Prototyping and Hardware Design.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

A Programming Environment for the Design of Complex High Speed ASICs.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Synthesis of pipelined DSP accelerators with dynamic scheduling.
IEEE Trans. Very Large Scale Integr. Syst., 1997

Hardware/software co-design of digital telecommunication systems.
Proc. IEEE, 1997

IP-based business conflicts.
IEEE Des. Test Comput., 1997

Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications.
Proceedings of the European Design and Test Conference, 1997

1996
CoWare - A design environment for heterogeneous hardware/software systems.
Des. Autom. Embed. Syst., 1996

Designing Systems On Silicon: A Digital Spread Spectrum Pager.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A Hilbert fractal codec for region oriented compression of color images.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

CoWare - a design environment for heterogenous hardware/software systems.
Proceedings of the conference on European design automation, 1996

Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Search space reduction through clustering in test generation.
Proceedings of the Proceedings EURO-DAC'95, 1995

1994
Design of heterogeneous ICs for mobile and personal communication systems.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

ASIC synthesis of a flexible 80 Mbit/s Reed-Solomon Codec.
Proceedings of the Proceedings EURO-DAC'94, 1994

1993
SMILE: A scalable microcontroller library element.
Microprocess. Microprogramming, 1993

High-level synthesis for real-time digital signal processing.
The Kluwer international series in engineering and computer science 216, Kluwer, ISBN: 978-0-7923-9313-9, 1993

1992
Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks.
Proceedings of the Synthesis for Control Dominated Circuits, 1992

Just in Time Scheduling.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991
Compiling Multi-Dimensional Data Streams into Distributed DSP ASIC Memory.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
Derivation of signal flow direction in MOS VLSI: an alternative.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989
Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1985
DIALOG: An Expert Debugging System for MOSVLSI Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985


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