Ivan Z. Milentijevic

Orcid: 0000-0002-6273-3379

According to our database1, Ivan Z. Milentijevic authored at least 21 papers between 1997 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Modular deep learning-based network intrusion detection architecture for real-world cyber-attack simulation.
Simul. Model. Pract. Theory, 2024

2020
Tiered Assignments in Lab Programming Sessions: Exploring Objective Effects on Students' Motivation and Performance.
IEEE Trans. Educ., 2020

2019
SpecINT: A framework for data integration over cheminformatics and bioinformatics RDF repositories.
Semantic Web, 2019

Cost Estimation of Blended Learning Course Delivery Through Public Cloud.
J. Univers. Comput. Sci., 2019

2016
All-Pairs Shortest Paths Algorithm for Regular 2D Mesh Topologies.
J. Univers. Comput. Sci., 2016

2015
Sparse Matrix Multiplication on Dataflow Engines.
Proceedings of the Parallel Processing and Applied Mathematics, 2015

Run-Time Machine Learning for HEVC/H.265 Fast Partitioning Decision.
Proceedings of the 2015 IEEE International Symposium on Multimedia, 2015

2014
Designing Intelligent Agent in Multilevel Game-Based Modules for E-Learning Computer Science Course.
Proceedings of the E-Learning Paradigms and Applications - Agent-based Approach, 2014

2013
Tropical algebra based framework for error propagation analysis in systolic arrays.
Appl. Math. Comput., 2013

2012
Pedagogical agent in Multimedia Interactive Modules for Learning - MIMLE.
Expert Syst. Appl., 2012

Yield Modeling for Error Tolerant and Partially Defect Tolerant Arrays.
Proceedings of the IEEE 19th International Conference and Workshops on Engineering of Computer-Based Systems, 2012

2010
Yield analysis of partial defect tolerant bit-plane array.
Comput. Math. Appl., 2010

2008
Configurable folded array for FIR filtering.
J. Syst. Archit., 2008

Version control in project-based learning.
Comput. Educ., 2008

2007
Project-based learning environment for special purpose DSP architectures.
Proceedings of the 9th International Symposium on Signal Processing and Its Applications, 2007

Area-time tradeoffs in h.264/AVC deblocking filter design for mobile devices.
Proceedings of the 9th International Symposium on Signal Processing and Its Applications, 2007

2005
Coefficient Bit Reordering Method for Configurable FIR Filtering on Folded Bit-plane Array.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2002
Folded semi-systolic fir filter architecture with changeable folding Factor.
Neural Parallel Sci. Comput., 2002

Folded Bit-Plane FIR Filter Architecture with Changeable Folding Factor.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

1998
Two-level pipelined systolic arrays for matrix-vector multiplication.
J. Syst. Archit., 1998

1997
Designing of Processor-Time Optimal Hexagonal Systolic Array for Matrix Multiplication.
Comput. Artif. Intell., 1997


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