Ivan Saraiva Silva

João P. dos S. Patrocinio

Proceedings of the XLVII Latin American Computing Conference, 2021

2020

Design Space Exploration of a Reconfigurable Accelerator in a Heterogeneous Multicore.

[BibT_eX]

[DOI]

Francisco Carlos Silva

José Carlos C. L. da Silva Filho

Ricardo Pezzuol Jacobi

Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

2019

A Method for Voltage Sag Source Location Using Clustering Algorithm and Decision Rule Labeling.

[BibT_eX]

[DOI]

Fábbio Anderson Silva Borges

Ricardo de Andrade Lira Rabelo

Roney Lira de Sales Santos

Proceedings of the International Joint Conference on Neural Networks, 2019

2016

Automatic labelling of clusters with discrete and continuous data using supervised machine learning.

[BibT_eX]

[DOI]

Joselito Mendes de Sousa

Lucas Araujo Lopes

Vinícius Ponte Machado

Francisco Carlos Silva Junior

Proceedings of the 35th International Conference of the Chilean Computer Science Society, 2016

Proposal and validation of an adaptable array for multi-core processors.

[BibT_eX]

[DOI]

Proceedings of the XLII Latin American Computing Conference, 2016

2015

An OpenCL-Compliant Multi-core Platform and Its Companion Compiler.

[BibT_eX]

[DOI]

Proceedings of the 2015 Brazilian Symposium on Computing Systems Engineering, 2015

IPNoSys II: A New Architecture for IPNoSys Programming Model.

[BibT_eX]

[DOI]

Thiago R. B. S. Soares

Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Scratchpad memory management using data-prefetching.

[BibT_eX]

[DOI]

Alba Sandyra Bezerra Lopes

Hildebrando Segundo

Proceedings of the 2015 Latin American Computing Conference, 2015

2012

A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2012

Operating System Support for IPNoSys.

[BibT_eX]

[DOI]

Sílvio R. F. de Araújo

CLEI Electron. J., 2012

A Methodology to Adapt Data Path Architectures to a MIPS-1 Model.

[BibT_eX]

[DOI]

Leonardo Augusto Casillo

Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

uVMP: Virtualizable multi-core platform.

[BibT_eX]

[DOI]

Proceedings of the 2012 XXXVIII Conferencia Latinoamericana En Informatica (CLEI), 2012

2011

DDR SDRAM Memory Controller for Digital TV Decoders.

[BibT_eX]

[DOI]

Hadley M. Siqueira

Alba Sandyra Bezerra Lopes

Márcio Eduardo Kreutz

Edgard de Faria Corrêa

Proceedings of the Brazilian Symposium on Computing System Engineering, 2011

An efficient memory hierarchy for full search motion estimation on high definition digital videos.

[BibT_eX]

[DOI]

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

ZONA - An adaptable NoC-based multiprocessor addressed to education on system-on-chip design.

[BibT_eX]

[DOI]

Leonardo Augusto Casillo

Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

2010

Exploring memory organization in virtual MP-SoC platforms.

[BibT_eX]

[DOI]

Márcio Eduardo Kreutz

Edgard de Faria Corrêa

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

2009

Processing while routing: a network-on-chipbased parallel system.

[BibT_eX]

[DOI]

M. Costa

IET Comput. Digit. Tech., 2009

Using NoC routers as processing elements.

[BibT_eX]

[DOI]

Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

2008

Using traditional loop unrolling to fit application on a new hybrid reconfigurable architecture.

[BibT_eX]

[DOI]

Monica Magalhães Pereira

Sílvio R. F. de Araújo

Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

2007

Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2007

RoSA: a reconfigurable stream-based architecture.

[BibT_eX]

[DOI]

Monica Magalhães Pereira

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Cache coherency communication cost in a NoC-based MPSoC platform.

[BibT_eX]

[DOI]

Gustavo Girão

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

2006

Implementation of a HDTV transport stream multiplexer based on ITU-T H.222.0 recommendation.

[BibT_eX]

[DOI]

Gustavo Girão

Sílvio R. F. de Araújo

Monica Magalhães Pereira

Proceedings of the 11th Brazilian Symposium on Multimedia and the Web, 2006

High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard.

[BibT_eX]

[DOI]

Roger Endrigo Carvalho Porto

José Luís Güntzel

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High Throughput Architecture of JPEG Compressor for Color Images Targeting FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

High throughput architecture for H.264/AVC forward transforms block.

[BibT_eX]

[DOI]

Roger Endrigo Carvalho Porto

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005

A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor.

[BibT_eX]

[DOI]

Roger Endrigo Carvalho Porto

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004

Parallel color space converters for JPEG image compression.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2004

When reconfigurable architecture meets network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters.

[BibT_eX]

[DOI]

Marcos R. Boschetti

Proceedings of the Field Programmable Logic and Application, 2004

A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications.

[BibT_eX]

[DOI]

Marcos R. Boschetti

Frederiko Stenio de Araújo

Proceedings of the 2004 Design, 2004

Papílio Cryptography Algorithm.

[BibT_eX]

[DOI]

Karla Darlene Nempomuceno Ramos

Benjamín René Callejas Bedregal

Proceedings of the Computational and Information Science, First International Symposium, 2004

2003

A New Hybrid Parallel/Reconfigurable Architecture: The X4CP32.

[BibT_eX]

[DOI]

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

X4CP32: A New Parallel/Reconfigurable General-Purpose Processor.

[BibT_eX]

[DOI]

Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 2003

X4CP32: A Coarse Grain General Purpose Reconfigurable Microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002

Techniques and Mechanisms for Dynamic Reconfiguration in an Image Processor.

[BibT_eX]

[DOI]

Marcos R. Boschetti

Alexandro M. S. Adário

Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Pipelined Entropy Coders for JPEG Compression.

[BibT_eX]

[DOI]

Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

2001

Pipelined Fast 2-D DCT Architecture for JPEG Image Compression.

[BibT_eX]

[DOI]