Ivan de Paúl

According to our database, Ivan de Paúl authored at least 17 papers between 2000 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results.

Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, Sebastià A. Bota, Jaume Segura

CoRR, 2024

Design Guidelines for β-Multiplier Current Reference Circuits.

Sebastià A. Bota, Rafel Perelló, Salvador Barceló, Ivan de Paúl, Jaume Segura, Jaume Verd

Proceedings of the 39th Conference on Design of Circuits and Integrated Systems, 2024

2023

A Compact Double-Exponential Circuit for Single Event Transient Emulation.

Sebastià A. Bota, Salvador Barceló, Gabriel Torrens, Rafel Perelló, Jaume Verd, Ivan de Paúl, Jaume Segura

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022

Fully Integrated Front-End CMOS-MEMS Transducer for Low-Cost Real-Time Breath Monitoring.

Rafel Perelló-Roig, Francisca Orvay, Ivan de Paúl, Jaume Verd, Sebastià A. Bota, Jaume Segura

Proceedings of the 2022 IEEE Sensors, Dallas, TX, USA, October 30 - Nov. 2, 2022, 2022

2018

Bistability in a CMOS-MEMS Thermally Tuned Microbeam Resonator.

Joan Barceló, Ivan de Paúl, Sebastià A. Bota, Jaume Segura, Jaume Verd

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2013

Accurate alpha soft error rate evaluation in SRAM memories.

Sebastià A. Bota, Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, L. A. Segura

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2009

Practical Hardware Implementation of Self-configuring Neural Networks.

José Luis Rosselló, Vincent Canals, Antoni Morro, Ivan de Paúl

Proceedings of the Advances in Neural Networks, 2009

Spiking Neural Network Self-configuration for Temporal Pattern Recognition Analysis.

José Luis Rosselló, Ivan de Paúl, Vincent Canals, Antoni Morro

Proceedings of the Artificial Neural Networks, 2009

2008

Self-configuring spiking neural networks.

José Luis Rosselló, Ivan de Paúl, Vincent Canals

IEICE Electron. Express, 2008

A simple CMOS chaotic integrated circuit.

José Luis Rosselló, Vincent Canals, Ivan de Paúl, Sebastià A. Bota, Antoni Morro

IEICE Electron. Express, 2008

Using stochastic logic for efficient pattern recognition analysis.

José Luis Rosselló, Vincent Canals, Ivan de Paúl, Jaume Segura

Proceedings of the International Joint Conference on Neural Networks, 2008

2007

Charge-based testing BIST for embedded memories.

Bartomeu Alorda, Ivan de Paúl, Jaume Segura

IET Comput. Digit. Tech., 2007

2006

A Fully CMOS Low-Cost Chaotic Neural Network.

José Luis Rosselló, Sebastià A. Bota, Vicent Canals, Ivan de Paúl, Jaume Segura

Proceedings of the International Joint Conference on Neural Networks, 2006

2004

A BIST-based Charge Analysis for Embedded Memories.

Bartomeu Alorda, Vicent Canals, Ivan de Paúl, Jaume Segura

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

2002

SEU fault injection in simulation environments: example of VHDL configuration on FPGA device.

Ivan de Paúl, Miquel Roca, Oscar Calvo, Raul Velazco

Proceedings of the 3rd Latin American Test Workshop, 2002

2001

Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments.

Ivan de Paúl, M. Rosales, Bartomeu Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000

On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor.

Bartomeu Alorda, Ivan de Paúl, Jaume Segura, T. Miller

Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000