Ivan Ciofi
Orcid: 0000-0003-1374-4116
According to our database1,
Ivan Ciofi
authored at least 21 papers
between 2000 and 2024.
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Bibliography
2024
Mitigating Line-Break Defectivity with a Sandwiched TiN or W Layer for Metal Pitch 18 NM Aspect Ratio 6 Semi-Damascene Interconnects.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Exploring the Reliability Limits for the Z-Pitch Scaling of Molybdenum Inter-Word Line Oxides in 3D NAND.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
Proceedings of the IEEE International Reliability Physics Symposium, 2024
BEOL tip-to-tip dielectric reliability characterization using a design-representative test structure.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
2023
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 2023 International Symposium on Physical Design, 2023
A pragmatic network-aware paradigm for system-level electromigration predictions at scale.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Towards accurate temperature prediction in BEOL for reliability assessment (Invited).
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2021
A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021
2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Method to assess the impact of LER and spacing variation on BEOL dielectric reliability using 2D-field simulations for <20nm spacing.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2017
LER and spacing variability on BEOL TDDB using E-field mapping: Impact of field acceleration.
Microelectron. Reliab., 2017
2016
Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation.
Microelectron. Reliab., 2016
2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
2014
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.
Proceedings of the 44th European Solid State Device Research Conference, 2014
2012
Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniques.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2001
PhD thesis, 2001
2000
Temperature controlled oven for low noise measurement systems [for electromigration characterization].
IEEE Trans. Instrum. Meas., 2000