Ivan Bietti
According to our database1,
Ivan Bietti
authored at least 10 papers
between 1997 and 2019.
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Bibliography
2019
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner.
IEEE J. Solid State Circuits, 2005
2004
A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications.
IEEE J. Solid State Circuits, 2004
2003
IEEE J. Solid State Circuits, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2000
A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1997
A 70-mW seventh-order filter with 7-50 MHz cutoff frequency and programmable boost and group delay equalization.
IEEE J. Solid State Circuits, 1997
A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo.
IEEE J. Solid State Circuits, 1997