Iuliana Bacivarov

According to our database, Iuliana Bacivarov authored at least 43 papers between 2002 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms.

Pier Stanislao Paolucci, Andrea Biagioni, Luis Gabriel Murillo, Frédéric Rousseau, Lars Schor, Laura Tosoratto, Iuliana Bacivarov, Robert Lajos Bücs, Clément Deschamps, Ashraf El Antably, Roberto Ammendola, Nicolas Fournel, Ottorino Frezza, Rainer Leupers, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Elena Pastorelli, Devendra Rai, Davide Rossetti, Francesco Simula

J. Syst. Archit., 2016

2014

EURETILE D7.3 - Dynamic DAL benchmark coding, measurements on MPI version of DPSNN-STDP (distributed plastic spiking neural net) and improvements to other DAL codes.

Pier Stanislao Paolucci, Iuliana Bacivarov, Devendra Rai, Lars Schor, Lothar Thiele, Hoeseok Yang, Elena Pastorelli, Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Francesco Simula, Laura Tosoratto, Piero Vicini

CoRR, 2014

EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems.

Lars Schor, Iuliana Bacivarov, Luis Gabriel Murillo, Pier Stanislao Paolucci, Frédéric Rousseau, Ashraf El Antably, Robert Buecs, Nicolas Fournel, Rainer Leupers, Devendra Rai, Lothar Thiele, Laura Tosoratto, Piero Vicini, Jan Weinstock

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

COOLIP: Simple yet effective job allocation for distributed thermally-throttled processors.

Pratyush Kumar, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Reliability-aware mapping optimization of multi-core systems with mixed-criticality.

Shin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCs.

Shin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

AdaPNet: Adapting process networks in response to resource variations.

Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele

Proceedings of the 2014 International Conference on Compilers, 2014

2013

Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-Chip.

Iuliana Bacivarov, Wolfgang Haid, Kai Huang, Lothar Thiele

Proceedings of the Handbook of Signal Processing Systems, 2013

Predictability for timing and temperature in multiprocessor system-on-chip platforms.

Lothar Thiele, Lars Schor, Iuliana Bacivarov, Hoeseok Yang

ACM Trans. Embed. Comput. Syst., 2013

Real-time worst-case temperature analysis with temperature-dependent parameters.

Hoeseok Yang, Iuliana Bacivarov, Devendra Rai, Jian-Jia Chen, Lothar Thiele

Real Time Syst., 2013

Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs.

Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele

J. Electron. Test., 2013

EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment

Pier Stanislao Paolucci, Iuliana Bacivarov, Gert Goossens, Rainer Leupers, Frédéric Rousseau, Christoph Schumacher, Lothar Thiele, Piero Vicini

CoRR, 2013

Reliable and Efficient Execution of Multiple Streaming Applications on Intel's SCC Processor.

Lars Schor, Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele

Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

Designing Applications with Predictable Runtime Characteristics for the Baremetal Intel SCC.

Devendra Rai, Lars Schor, Nikolay Stoimenov, Iuliana Bacivarov, Lothar Thiele

Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

Expandable process networks to efficiently specify and explore task, data, and pipeline parallelism.

Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele

Proceedings of the International Conference on Compilers, 2013

2012

Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications.

Kai Huang, Wolfgang Haid, Iuliana Bacivarov, Matthias Keller, Lothar Thiele

ACM Trans. Embed. Comput. Syst., 2012

Worst-case temperature analysis for different resource models.

Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele

IET Circuits Devices Syst., 2012

Worst-Case Temperature Guarantees for Real-Time Applications on Multi-core Systems.

Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele

Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012

Fast worst-case peak temperature evaluation for real-time applications on multi-core systems.

Lars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele

Proceedings of the 13th Latin American Test Workshop, 2012

PRO3D: programming for future 3D manycore architectures.

Christian Fabre, Iuliana Bacivarov, Eth Zürich, Ananda Basu, Martino Ruggiero, David Atienza, Eric Flamand

Proceedings of the 2012 Interconnection Network Architecture, 2012

Multi-objective mapping optimization via problem decomposition for many-core systems.

Shin-Haeng Kang, Hoeseok Yang, Lars Schor, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele

Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

MAMOT: Memory-Aware Mapping Optimization Tool for MPSoC.

Olivera Jovanovic, Peter Marwedel, Iuliana Bacivarov, Lothar Thiele

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Scenario-based design flow for mapping streaming applications onto on-chip many-core systems.

Lars Schor, Iuliana Bacivarov, Devendra Rai, Hoeseok Yang, Shin-Haeng Kang, Lothar Thiele

Proceedings of the 15th International Conference on Compilers, 2012

Power agnostic technique for efficient temperature estimation of multicore embedded systems.

Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele

Proceedings of the 15th International Conference on Compilers, 2012

2011

Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study.

Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Thermal-Aware Task Assignment for Real-Time Applications on Multi-Core Systems.

Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele

Proceedings of the Formal Methods for Components and Objects, 10th International Symposium, 2011

PRO3D, Programming for Future 3D Manycore Architectures: Project's Interim Status.

Christian Fabre, Iuliana Bacivarov, Ananda Basu, Martino Ruggiero, David Atienza, Eric Flamand, Jean-Pierre Krimm, Julien Mottin, Lars Schor, Pratyush Kumar, Hoeseok Yang, Devesh B. Chokshi, Lothar Thiele, Saddek Bensalem, Marius Bozga, Luca Benini, Mohamed M. Sabry, Yusuf Leblebici, Giovanni De Micheli, Diego Melpignano

Proceedings of the Formal Methods for Components and Objects, 10th International Symposium, 2011

Worst-case temperature analysis for real-time systems.

Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Jian-Jia Chen, Lothar Thiele

Proceedings of the Design, Automation and Test in Europe, 2011

Thermal-aware system analysis and software synthesis for embedded multi-processors.

Lothar Thiele, Lars Schor, Hoeseok Yang, Iuliana Bacivarov

Proceedings of the 48th Design Automation Conference, 2011

Mapping of applications to MPSoCs.

Peter Marwedel, Jürgen Teich, Georgia Kouveli, Iuliana Bacivarov, Lothar Thiele, Soonhoi Ha, Chanhee Lee, Qiang Xu, Lin Huang

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010

Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-Chip.

Iuliana Bacivarov, Wolfgang Haid, Kai Huang, Lothar Thiele

Proceedings of the Handbook of Signal Processing Systems, 2010

2009

Multiprocessor SoC software design flows.

Wolfgang Haid, Kai Huang, Iuliana Bacivarov, Lothar Thiele

IEEE Signal Process. Mag., 2009

A modular fast simulation framework for stream-oriented MPSoC.

Kai Huang, Iuliana Bacivarov, Jun Liu, Wolfgang Haid

Proceedings of the IEEE Fourth International Symposium on Industrial Embedded Systems, 2009

Generation and calibration of compositional performance analysis models for multi-processor systems.

Wolfgang Haid, Matthias Keller, Kai Huang, Iuliana Bacivarov, Lothar Thiele

Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Efficient execution of Kahn process networks on multi-processor systems using protothreads and windowed FIFOs.

Wolfgang Haid, Lars Schor, Kai Huang, Iuliana Bacivarov, Lothar Thiele

Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009

2008

Scalably distributed SystemC simulation for embedded applications.

Kai Huang, Iuliana Bacivarov, Fabian Hugelshofer, Lothar Thiele

Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008

2007

Mapping Applications to Tiled Multiprocessor Embedded Systems.

Lothar Thiele, Iuliana Bacivarov, Wolfgang Haid, Kai Huang

Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007

2006

Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application.

Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005

ChronoSym: a new approach for fast and accurate SoC cosimulation.

Iuliana Bacivarov, Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya

Int. J. Embed. Syst., 2005

Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration.

Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed Amine Jerraya

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003

Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer.

Sungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya

Proceedings of the 2003 Design, 2003

Multi-Level Software Validation for NoC.

Sungjoo Yoo, Gabriela Nicolescu, Iuliana Bacivarov, Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya

Proceedings of the Networks on Chip, 2003

2002

Timed HW-SW cosimulation using native execution of OS and application SW.

Iuliana Bacivarov, Sungjoo Yoo, Ahmed Amine Jerraya

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002