Itsujiro Arita

According to our database1, Itsujiro Arita authored at least 23 papers between 1980 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2008
Navilite: a Lightweight Indoor Location-Aware Mobile Navigation Service for the Handicapped and the Elderly.
J. Mobile Multimedia, 2008

2007
An Indoor Location-Aware Mobile Navigation Service for the Handicapped and the Elderly.
Proceedings of the MoMM'2007, 2007

2003
A trace-level value predictor for Contrail processors.
SIGARCH Comput. Archit. News, 2003

Combining variable latency pipeline with instruction reuse for execution latency reduction.
Syst. Comput. Jpn., 2003

2002
The development and evaluation of SHOKE2000: The PCI-based FPGA card.
Syst. Comput. Jpn., 2002

The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

Reducing Energy Consumption via Low-Cost Value Prediction.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Low-Cost Value Predictors Using Frequent Value Locality.
Proceedings of the High Performance Computing, 4th International Symposium, 2002

Simplifying Instruction Issue Logic in Superscalar Processors.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2001
Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

In Search of Efficient Reliable Processor Design.
Proceedings of the 2001 International Conference on Parallel Processing, 2001

Evaluating the Performance of a DSM Cluster with Improved Communication Subsystem.
Proceedings of the 15th International Conference on Information Networking, 2001

Influence of Compiler Optimizations on Value Prediction.
Proceedings of the High-Performance Computing and Networking, 9th International Conference, 2001

Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

Tolerating Transient Faults through an Instruction Reissue Mechanism.
Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, 2001

2000
The KIT COSMOS Processor: Introducing CONDOR.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Comprehensive Evaluation of an Instruction Reissue Mechanism.
Proceedings of the 5th International Symposium on Parallel Architectures, 2000

Table size reduction for data value predictors by exploiting narrow width values.
Proceedings of the 14th international conference on Supercomputing, 2000

Partial Resolution in Data Value Predictors.
Proceedings of the 2000 International Conference on Parallel Processing, 2000

Sending an Image to a Large Number of Nodes in Short Time using TCP.
Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000

1999
Towards a Portable Cluster Computing Environment Supporting Single System Image.
Proceedings of the 1999 International Conference on Parallel Processing Workshops, 1999

1986
Performance evaluation of the binary tree access mechanism in mimd type parallel computers.
Syst. Comput. Jpn., 1986

1980
Intelligent console - A universal user interface of a computer system.
Proceedings of the Operating Systems Engineering: Proceedings of the 14th IBM Computer SCience Symposium, 1980


  Loading...