Itaru Hida
According to our database1,
Itaru Hida
authored at least 3 papers
between 2013 and 2016.
Collaborative distances:
Collaborative distances:
Timeline
2013
2014
2015
2016
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1
2
1
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2016
A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2014
A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013