Itamar Levi
Orcid: 0000-0002-5591-5799Affiliations:
- Bar-Ilan University, Ramat Gan, Israel
According to our database1,
Itamar Levi
authored at least 58 papers
between 2012 and 2024.
Collaborative distances:
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Bibliography
2024
Revealing the Secrets of Radio Embedded Systems: Extraction of Raw Information via RF.
IEEE Trans. Inf. Forensics Secur., 2024
CrISA-X: Unleashing Performance Excellence in Lightweight Symmetric Cryptography for Extendable and Deeply Embedded Processors.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024
Consolidated Linear Masking (CLM): Generalized Randomized Isomorphic Representations, Powerful Degrees of Freedom and Low(er)-cost.
IACR Cryptol. ePrint Arch., 2024
EMI Shielding for Use in Side-Channel Security: Analysis, Simulation and Measurements.
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
Providing Integrity for Authenticated Encryption in the Presence of Joint Faults and Leakage.
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
Refined Analytical EM Model of IC-Internal Shielding for Hardware-Security and Intra-Device Simulative Framework.
IEEE Access, 2024
IEEE Access, 2024
Proceedings of the Security and Cryptography for Networks - 14th International Conference, 2024
2023
Analytical Side Channel EM Models, Extending Simulation Abilities for ICs, and Linking Physical Models to Cryptographic Metrics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
MaskSIMD-lib: on the performance gap of a generic C optimized assembly and wide vector extensions for masked software with an Ascon-p test case.
J. Cryptogr. Eng., September, 2023
An In-Depth Evaluation of Externally Amplified Coupling (EAC) Attacks - A Concrete Threat for Masked Cryptographic Implementations.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
Revealing the Secrets of Radio-Enabled Embedded Systems: on extraction of raw information from any on-board signal through RF.
IACR Cryptol. ePrint Arch., 2023
SCMA: Plaintext Classification Assisted Side Channel Spectral Modulation Attacks. Towards Noise-insensitive SCA Attacks...
IACR Cryptol. ePrint Arch., 2023
Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow.
IEEE Access, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Exploring Multi-Parameter Optimization of Automated HLS Tools and the Difficulty of Setting Complex Constraints.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
2022
On the Performance Gap of a Generic C Optimized Assembler and Wide Vector Extensions for Masked Software with an Ascon-{\it{p}} test case.
IACR Cryptol. ePrint Arch., 2022
Fully-Digital Randomization Based Side-Channel Security - Toward Ultra-Low Cost-per-Security.
IEEE Access, 2022
2021
IEEE Trans. Computers, 2021
Cryptogr., 2021
The Cost of a True Random Bit - On the Electronic Cost Gain of ASIC Time-Domain-Based TRNGs.
Cryptogr., 2021
Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads.
IEEE Access, 2021
2020
IACR Trans. Symmetric Cryptol., 2020
Spook: Sponge-Based Leakage-Resistant Authenticated Encryption with a Masked Tweakable Block Cipher.
IACR Trans. Symmetric Cryptol., 2020
IEEE Trans. Circuits Syst., 2020
Int. J. Circuit Theory Appl., 2020
How Bad Are Bad Templates? Optimistic Design-Stage Side-Channel Security Evaluation and its Cost.
Cryptogr., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Reducing a Masked Implementation's Effective Security Order with Setup Manipulations And an Explanation Based on Externally-Amplified Couplings.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI.
IEEE J. Solid State Circuits, 2019
A security oriented transient-noise simulation methodology: Evaluation of intrinsic physical noise of cryptographic designs.
Integr., 2019
Proceedings of the 10th IFIP International Conference on New Technologies, 2019
Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Proceedings of the 2018 New Generation of CAS, 2018
Embedded randomness and data dependencies design paradigm: Advantages and challenges.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Access, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2013
Microelectron. J., 2013
IEEE Access, 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012