Isuru Nawinne

According to our database, Isuru Nawinne authored at least 10 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2024

Multimodal Deep Convolutional Neural Network Pipeline for AI-Assisted Early Detection of Oral Cancer.

G. A. I. Devindi, D. M. D. R. Dissanayake, S. N. Liyanage, F. B. A. H. Francis, M. B. D. Pavithya, N. S. Piyarathne, P. V. K. S. Hettiarachchi, R. M. S. G. K. Rasnayaka, Ruwan Duminda Jayasinghe, Roshan G. Ragel, Isuru Nawinne

IEEE Access, 2024

2023

Mixed-Reality Based Multi-Agent Robotics Framework for Artificial Swarm Intelligence Experiments.

Dilshani Karunarathna, Nuwan Jaliyagoda, Ganindu Jayalath, Janaka Alawatugoda, Roshan G. Ragel, Isuru Nawinne

IEEE Access, 2023

RV32IMF Five-Stage Pipeline Implementation with Interrupt and Random Number Generation Units.

Dinindu Thilakarathna, Heshan Dissanayake, Buddhi Perera, Roshan G. Ragel, Isuru Dasanayake, Mahanama Wickramasinghe, Isuru Nawinne

Proceedings of the 17th IEEE International Conference on Industrial and Information Systems, 2023

2019

An Ensemble Learning Approach for Electrocardiogram Sensor Based Human Emotion Recognition.

Theekshana Dissanayake, Yasitha Rajapaksha, Roshan G. Ragel, Isuru Nawinne

Sensors, 2019

Non-contact Infant Sleep Apnea Detection.

Gihan Jayatilaka, Harshana Weligampola, Suren Sritharan, Pankayraj Pathmanathan, Roshan G. Ragel, Isuru Nawinne

Proceedings of the 14th Conference on Industrial and Information Systems, 2019

2016

Hardware accelerated cache design space exploration for application specific MPSoCs.

Isuru Nawinne

PhD thesis, 2016

Switchable cache: utilising dark silicon for application specific cache optimisations.

Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Sri Parameswaran

IET Comput. Digit. Tech., 2016

2015

Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs.

Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Swarnalatha Radhakrishnan, Sri Parameswaran

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

Hardware-based fast exploration of cache hierarchies in application specific MPSoCs.

Isuru Nawinne, Josef Schneider, Haris Javaid, Sri Parameswaran

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs.

Jude Angelo Ambrose, Isuru Nawinne, Sri Parameswaran

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013