Israel Koren
Orcid: 0000-0003-2741-7108
According to our database1,
Israel Koren
authored at least 240 papers
between 1977 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1991, "For contributions to the field of fault-tolerant VLSI systems.".
Timeline
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On csauthors.net:
Bibliography
2024
Mix-Zones as an Effective Privacy Enhancing Technique in Mobile and Vehicular Ad-hoc Networks.
ACM Comput. Surv., December, 2024
2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
Adaptive workload adjustment for cyber-physical systems using deep reinforcement learning.
Sustain. Comput. Informatics Syst., 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
IEEE Trans. Sustain. Comput., 2020
Enhancing dependability and energy efficiency of cyber-physical systems by dynamic actuator derating.
Sustain. Comput. Informatics Syst., 2020
Using digital imagers to characterize the dependence of energy and area distributions of SEUs on elevation.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020
2019
Enhancing Vehicular Anonymity in ITS: A New Scheme for Mix Zones and Their Placement.
IEEE Trans. Veh. Technol., 2019
Proceedings of the Image Sensors and Imaging Systems 2019, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
2018
Proceedings of the 26th Euromicro International Conference on Parallel, 2018
Detecting and counteracting benign faults and malicious attacks in cyber physical systems.
Proceedings of the 7th Mediterranean Conference on Embedded Computing, 2018
Energy and Dependability Enhancement by Dynamic Actuator Derating in Cyber-Physical Systems.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018
Proceedings of the Image Sensors and Imaging Systems 2018, 2018
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018
Adaptive and polymorphic VLIW processor to optimize fault tolerance, energy consumption, and performance.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
2017
ACM Trans. Embed. Comput. Syst., 2017
Sustain. Comput. Informatics Syst., 2017
ACM Comput. Surv., 2017
Proceedings of the International Conference for High Performance Computing, 2017
Keynote speech: IGSC 2017: Green computing through adaptive multi-core architectures.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017
Proceedings of the Image Sensors and Imaging Systems 2017, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
CAROL-FI: an Efficient Fault-Injection Tool for Vulnerability Evaluation of Modern HPC Parallel Accelerators.
Proceedings of the Computing Frontiers Conference, 2017
Proceedings of the Computing Frontiers Conference, 2017
2016
IEEE Trans. Parallel Distributed Syst., 2016
J. Low Power Electron., 2016
Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Improving performance per Watt of non-monotonic Multicore Processors via bottleneck-based online program phase classification.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the Image Sensors and Imaging Systems 2016, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016
2015
ACM Trans. Embed. Comput. Syst., 2015
Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Improving processor lifespan and energy consumption using DVFS based on ILP monitoring.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015
Proceedings of the Image Sensors and Imaging Systems 2015, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks.
IEEE Trans. Emerg. Top. Comput., 2014
Int. J. Embed. Syst., 2014
Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014
Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric Multicores.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the Image Sensors and Imaging Systems 2014, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
J. Low Power Electron., 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
A study on polymorphing superscalar processor dynamically to improve power efficiency.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the International Conference on Computing, Networking and Communications, 2013
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Empirical formula for rates of hot pixel defects based on pixel size, sensor area, and ISO.
Proceedings of the Sensors, 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013
2012
Interaction Between Fault Attack Countermeasures and the Resistance Against Power Analysis Attacks.
Proceedings of the Fault Analysis in Cryptography, 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing.
ACM Trans. Design Autom. Electr. Syst., 2012
Special Issue: Selected papers from the 2011 IEEE International Green Computing Conference (IGCC 2011).
Sustain. Comput. Informatics Syst., 2012
Fault Injection Attacks on Cryptographic Devices: Theory, Practice, and Countermeasures.
Proc. IEEE, 2012
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
A Study of the Impact of Computational Delays in Missile Interception Systems.
Proceedings of the ICINCO 2012 - Proceedings of the 9th International Conference on Informatics in Control, Automation and Robotics, Volume 1, Rome, Italy, 28, 2012
Cost Functions for Scheduling Tasks in Cyber-physical Systems.
Proceedings of the ICINCO 2012 - Proceedings of the 9th International Conference on Informatics in Control, Automation and Robotics, Volume 1, Rome, Italy, 28, 2012
Proceedings of the 2012 International Green Computing Conference, 2012
Projecting the rate of in-field pixel defects based on pixel size, sensor area, and ISO.
Proceedings of the Sensors, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
2011
Utilization-Based Resource Partitioning for Power-Performance Efficiency in SMT Processors.
IEEE Trans. Parallel Distributed Syst., 2011
Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-threshold Devices through an Example of a 65nm AES Implementation.
Proceedings of the RFID. Security and Privacy - 7th International Workshop, 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the Sensors, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010
A study on performance benefits of core morphing in an asymmetric multicore processor.
Proceedings of the 28th International Conference on Computer Design, 2010
Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Countermeasures against fault attacks on software implemented AES: effectiveness and cost.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010
2009
Proceedings of the Digital Photography V, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
2008
Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008
2007
IEEE Trans. Parallel Distributed Syst., 2007
IEEE Trans. Computers, 2007
J. Low Power Electron., 2007
J. Low Power Electron., 2007
Proceedings of the Fifth Annual IEEE International Conference on Pervasive Computing and Communications, 2007
Proceedings of the Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2007
Proceedings of the Digital Photography III, San Jose, CA, USA, January 29-30, 2007, 2007
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2006
Guest Editors' Introduction: Special Section on Fault Diagnosis and Tolerance in Cryptography.
IEEE Trans. Computers, 2006
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the IEEE International Geoscience & Remote Sensing Symposium, 2006
Software-Based Adaptive and Concurrent Self-Testing in Programmable Network Interfaces.
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 2005 International Conference on Compilers, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Synthesis of Saturating Counters Using Traditional and Non-Traditional Basic Counters.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005
2004
IEEE Des. Test Comput., 2004
Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004
Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Workshop on Fault Diagnosis and Tolerance in Cryptography.
Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June, 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Combining compiler and runtime IPC predictions to reduce energy in next generation architectures.
Proceedings of the First Conference on Computing Frontiers, 2004
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004
Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004
2003
Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters.
IEEE Trans. Very Large Scale Integr. Syst., 2003
Cool-Cache: A compiler-enabled energy efficient data caching framework for embedded/multimedia processors.
ACM Trans. Embed. Comput. Syst., 2003
Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard.
IEEE Trans. Computers, 2003
Optimizing the Yield of VLSI Circuits.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003
Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003
Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003
2002
Filtering Random Graphs to Synthesize Interconnection Networks with Multiple Objectives.
IEEE Trans. Parallel Distributed Syst., 2002
Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEEE Comput. Archit. Lett., 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
Using Rational Approximations for Evaluating the Reliablity of Highly Reliable Systems.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002
A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002
2001
Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations.
IEEE Trans. Computers, 2001
Simul., 2001
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
2000
J. Supercomput., 2000
IEEE Trans. Computers, 2000
IEEE Trans. Computers, 2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
Power-Aware Replication of Data Structures in Distributed Embedded Real-Time Systems.
Proceedings of the Parallel and Distributed Processing, 2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
1999
J. Syst. Archit., 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999
1998
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
1997
IEEE Trans. Very Large Scale Integr. Syst., 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems.
Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997
1996
A Mean Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques.
Int. J. Parallel Program., 1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
1995
IEEE Trans. Neural Networks, 1995
Architecture and technology tradeoffs in the design of next-generation multiprocessor servers.
Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995
1994
IEEE Trans. Very Large Scale Integr. Syst., 1994
Connectivity and performance tradeoffs in the cascade correlation learning architecture.
IEEE Trans. Neural Networks, 1994
Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations With Bounded Carry Propagation Chains.
IEEE Trans. Computers, 1994
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis.
IEEE Trans. Computers, 1994
Proceedings of the Parallel Architectures and Compilation Techniques, 1994
An Algorithm for Area and Delay Optimization of Sequential Machines through Decomposition.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994
The Effect of Wire Length Minimization on Yield.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
A Yield Study of VLSI Adders.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
1993
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits.
IEEE Trans. Computers, 1993
Neural Comput., 1993
Discret. Appl. Math., 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
An Interactive Yield Estimator as a VLSI CAD Tool.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
Does the Floorplan of a Chip Affect Its Yield?
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
Topological Optimization of PLAs for Yield Enhancement.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
Proceedings of the International Conference on Application-Specific Array Processors, 1993
Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993
Computer arithmetic algorithms.
Prentice Hall, ISBN: 978-0-13-151952-7, 1993
1992
Estimating the Potential Parallelism and Pipelining of Algorithms for Data Flow Machines.
J. Parallel Distributed Comput., 1992
1991
Discrete and Continuous Models for the Performance of Reconfigurable Multistage Systems.
IEEE Trans. Computers, 1991
J. Parallel Distributed Comput., 1991
Using Simulated Annealing for Mapping Algorithms onto Data Driven Arrays.
Proceedings of the International Conference on Parallel Processing, 1991
1990
Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations.
IEEE Trans. Computers, 1990
1989
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
1988
IEEE J. Solid State Circuits, June, 1988
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988
Math. Syst. Theory, 1988
Proceedings of the 8th International Conference on Distributed Computing Systems, 1988
1987
IEEE Trans. Computers, 1987
IEEE Trans. Computers, 1987
IEEE Trans. Computers, 1987
1986
IEEE Trans. Computers, 1986
Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems.
Proc. IEEE, 1986
1985
Evaluating the Cost-Effectiveness of Switches in Processor Array Architectures.
Proceedings of the International Conference on Parallel Processing, 1985
1984
IEEE Trans. Computers, 1984
1983
A Direct Mapping of Algorithms onto VLSI Processing Arrays Based on the Data Flow Approach.
Proceedings of the International Conference on Parallel Processing, 1983
1981
IEEE Trans. Computers, 1981
Proceedings of the 8th Annual Symposium on Computer Architecture, 1981
1980
IEEE Trans. Computers, 1980
1979
Reliability Analysis of <i>N</i>-Modular Redundancy Systems with Intermittent and Permanent Faults.
IEEE Trans. Computers, 1979
IEEE Trans. Computers, 1979
1978
IEEE Trans. Computers, 1978
Proceedings of the 4th IEEE Symposium on Computer Arithmetic, 1978
1977
IEEE Trans. Computers, 1977