Ismael Seidel

According to our database1, Ismael Seidel authored at least 27 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Rate-Distortion and Complexity Analysis of Fast Video Encoders.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023
Energy and Computing Assessment of Video Processing Kernels on CPU and FPGA platforms.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Low-Energy and Reduced-Area Hardware Architecture for the Versatile Video Coding FME.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

A New Approach to Video Coding Leveraging Hybrid Coding and Video Frame Interpolation.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Neural Architecture Search for Tiny Detectors of Inter-beat Intervals.
Proceedings of the 31st European Signal Processing Conference, 2023

2022
Exploring the Impacts of Multiple Kernel Sizes of Gaussian Filters Combined to Approximate Computing in Canny Edge Detection.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

2021
SAD or SATD? How the Distortion Metric Impacts a Fractional Motion Estimation VLSI Architecture.
Proceedings of the 23rd International Workshop on Multimedia Signal Processing, 2021

Hardware-Friendly Search Patterns for the Versatile Video Coding Fractional Motion Estimation.
Proceedings of the 23rd International Workshop on Multimedia Signal Processing, 2021

Design of Energy-Efficient Gaussian Filters by Combining Refactoring and Approximate Adders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Memory-Friendly Segmentation Refinement for Video-Based Point Cloud Compression.
Proceedings of the 2021 IEEE International Conference on Image Processing, 2021

Relying on a Rate Constraint to Reduce Motion Estimation Complexity.
Proceedings of the IEEE International Conference on Acoustics, 2021

2020
Standalone Rate-Distortion FME Architecture.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

2018
On the calculation reuse in hadamard-based SATD.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Coding- and Energy-Efficient FME Hardware Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

On HEVC Robustness to Integer Motion Estimation Pruning.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Block matching hardware architecture for SATD-based successive elimination.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Improving the energy efficiency of a low-area SATD hardware architecture using fine grain PDE.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

2016
Squarer exploration for energy-efficient sum of squared differences.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Energy-efficient SATD for beyond HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Rate-constrained successive elimination of Hadamard-based SATDs.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Coarse grain partial distortion elimination for Hadamard ME in HEVC.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiency.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

2014
Energy-Efficient Hadamard-Based SATD Architectures.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Exploring pel decimation to trade off between energy and quality in video coding.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

2013
On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

A low-power configurable VLSI architecture for sum of absolute differences calculation.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Quality assessment of subsampling patterns for pel decimation targeting high definition video.
Proceedings of the 2013 IEEE International Conference on Multimedia and Expo, 2013


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