Ishwar Parulkar

According to our database, Ishwar Parulkar authored at least 20 papers between 1994 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2010

Panel: Reliability of data centers: Hardware vs. software.

Mehdi Baradaran Tahoori, Ishwar Parulkar, Dan Alexandrescu, Kevin Granlund, Allan Silburt, Bapi Vinnakota

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor.

Georgios K. Konstadinidis, Marc Tremblay, Shailender Chaudhry, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar

IEEE J. Solid State Circuits, 2009

Comprehensive Approach to High-Performance Server Chipset Debug.

Ishwar Parulkar, Babu Turumella

IEEE Des. Test Comput., 2009

Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors.

Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Ishwar Parulkar

Proceedings of the 14th IEEE European Test Symposium, 2009

2008

DFX of a 3^rd Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor.

Ishwar Parulkar, Sriram Anandakumar, Gaurav Agarwal, Gordon Liu, Krishna Rajan, Frank Chiu, Rajesh Pendurkar

Proceedings of the 2008 IEEE International Test Conference, 2008

Implementation of a Third-Generation 16-Core 32-Thread Chip-Multithreading SPARCs® Processor.

Georgios K. Konstadinidis, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Silent Data Corruption - Myth or reality?

Cristian Constantinescu, Ishwar Parulkar, R. Harper, Sarah Michalak

Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

2005

Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems.

Iain Robertson, Graham Hetherington, Tom Leslie, Ishwar Parulkar, Ronald Lesnikoski

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in field.

Ishwar Parulkar, Dawei Huang, Leandro Chua Jr., Drew Doblar

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and Systems.

Ishwar Parulkar, Robert Cypher

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

2003

Latch Divergency In Microprocessor Failure Analysis.

Peter Dahlgren, Paul Dickinson, Ishwar Parulkar

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC^TM Chip Multi-Processors.

Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Introducing redundant computations in RTL data paths for reducing BIST resources.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

ACM Trans. Design Autom. Electr. Syst., 2001

1998

Estimation of BIST Resources During High-Level Synthesis.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

J. Electron. Test., 1998

Allocation Techniques for Reducing BIST Area Overhead of Data Paths.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

J. Electron. Test., 1998

Scheduling and Module Assignment for Reducing Bist Resources.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 1998 Design, 1998

Introducing Redundant Computations in a Behavior for Reducing BIST Resources.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 35th Conference on Design Automation, 1998

1996

Lower Bounds on Test Resources for Scheduled Data Flow Graphs.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 33st Conference on Design Automation, 1996

1995

Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead.

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the 32st Conference on Design Automation, 1995

1994

Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST.

Ishwar Parulkar, Melvin A. Breuer, Charles Njinda

Proceedings of the 31st Conference on Design Automation, 1994