Ishan G. Thakkar
Orcid: 0000-0002-7289-1530
According to our database1,
Ishan G. Thakkar
authored at least 52 papers
between 2014 and 2024.
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Bibliography
2024
ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024
An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects.
ACM J. Emerg. Technol. Comput. Syst., April, 2024
HEANA: A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference.
CoRR, 2024
Scaling Analog Photonic Accelerators for Byte-Size, Integer General Matrix Multiply (GEMM) Kernels.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
2023
A Silicon Nitride Microring Modulator for High-Performance Photonic Integrated Circuits.
CoRR, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
An Optical XNOR-Bitcount Based Accelerator for Efficient Inference of Binary Neural Networks.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
A Polymorphic Electro-Optic Logic Gate for High-Speed Reconfigurable Computing Circuits.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
SCONNA: A Stochastic Computing Based Optical Accelerator for Ultra-Fast, Energy-Efficient Inference of Integer-Quantized CNNs.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023
High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
2022
Photonic Reconfigurable Accelerators for Efficient Inference of CNNs With Mixed-Sized Tensors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion.
IEEE Micro, 2022
Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study.
ACM J. Emerg. Technol. Comput. Syst., 2022
A Silicon Nitride Microring Based High-Speed, Tuning-Efficient, Electro-Refractive Modulator.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
ODIN: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-Situ Neural Network Processing in Phase Change RAM.
CoRR, 2021
Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir Computing.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Design Exploration and Scalability Analysis of a CMOS-Integrated, Polymorphic, Nanophotonic Arithmetic-Logic Unit.
Proceedings of the SenSys '21: The 19th ACM Conference on Embedded Networked Sensor Systems, Coimbra, Portugal, November 15, 2021
ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
2020
Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration.
CoRR, 2020
PROTEUS: Rule-Based Self-Adaptation in Photonic NoCs for Loss-Aware Co-Management of Laser Power and Performance.
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020
Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Redesigning Photonic Interconnects with Silicon-on-Sapphire Device Platform for Ultra-Low-Energy On-Chip Communication.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
2019
A scalable stochastic number generator for phase change memory based in-memory stochastic processing: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019
Mitigating inter-channel crosstalk non-uniformity in microring filter arrays of photonic NoCs: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019
Proceedings of the 2019 International Conference on Compliers, 2019
2018
HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCs.
IEEE Trans. Very Large Scale Integr. Syst., 2018
LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-Chip.
IEEE Trans. Multi Scale Comput. Syst., 2018
DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018
Mitigating the Energy Impacts of VBTI Aging in Photonic Networks-on-Chip Architectures with Multilevel Signaling.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing.
Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017
Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017
2016
Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects.
Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016
Run-time laser power management in photonic NoCs with on-chip semiconductor optical amplifiers.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
Process variation aware crosstalk mitigation for DWDM based photonic NoC architectures.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
PICO: mitigating heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Mitigation of homodyne crosstalk noise in silicon photonic NoC architectures with tunable decoupling.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
2015
3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead.
IEEE Trans. Multi Scale Comput. Syst., 2015
IEEE Des. Test, 2015
A novel 3D graphics DRAM architecture for high-performance and low-energy memory accesses.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
2014
3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014