Isamu Asano

According to our database1, Isamu Asano authored at least 3 papers between 1996 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2024
Materials Engineering for High Performance Ferroelectric Memory.
Proceedings of the IEEE International Memory Workshop, 2024

2009
A novel on-chip voltage generator for low voltage DRAMs and PRAMs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

1996
A 29-ns 64-Mb DRAM with hierarchical array architecture.
IEEE J. Solid State Circuits, 1996


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