Isamu Asano

According to our database, Isamu Asano authored at least 3 papers between 1996 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Materials Engineering for High Performance Ferroelectric Memory.

Ashonita Chavan, Adharsh Rajagopal, Yixin Yan, Isamu Asano, Devanarayanan Ettisserry, Vassil Antonov, Giorgio Servalli, Alessandro Calderoni, Nirmal Ramaswamy

Proceedings of the IEEE International Memory Workshop, 2024

2009

A novel on-chip voltage generator for low voltage DRAMs and PRAMs.

Tatsuya Matano, Koji Sato, Kiyoshi Nakai, Isamu Asano

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

1996

A 29-ns 64-Mb DRAM with hierarchical array architecture.

Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato

IEEE J. Solid State Circuits, 1996