Isabel C. Teixeira

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

Aging-Aware Power or Frequency Tuning With Predictive Fault Detection.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2012

The influence of clock-gating on NBTI-induced delay degradation.

[BibT_eX]

[DOI]

Jackson Pachito

Celestino V. Martins

Marcelino Bicho Dos Santos

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

2011

On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications.

[BibT_eX]

[DOI]

J. Low Power Electron., 2011

Lower <i>V</i><sub>DD</sub> Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing.

[BibT_eX]

[DOI]

J. Low Power Electron., 2011

Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects.

[BibT_eX]

[DOI]

María Dolores Valdés

María José Moure

Proceedings of the 12th Latin American Test Workshop, 2011

On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications.

[BibT_eX]

[DOI]

Proceedings of the 12th Latin American Test Workshop, 2011

Modeling the effect of process variations on the timing response of nanometer digital circuits.

[BibT_eX]

[DOI]

Proceedings of the 12th Latin American Test Workshop, 2011

Performance Failure Prediction Using Built-In Delay Sensors in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010

Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance.

[BibT_eX]

[DOI]

Lucía Costas

J. Low Power Electron., 2010

Low-sensitivity to process variations aging sensor for automotive safety-critical applications.

[BibT_eX]

[DOI]

Letícia Maria Veiras Bolzani

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Automatic Configuration of a Medical Imaging System to Unknown Delays in Synchronous Input Data Channels.

[BibT_eX]

[DOI]

Pedro Miguel Rodrigues

José C. Silva

Pedro Lousã

João Varela

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Predictive error detection by on-line aging monitoring.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Investigating the Use of BICS to detect resistive-open defects in SRAMs.

[BibT_eX]

[DOI]

Raul Chipana

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Programmable aging sensor for automotive safety-critical applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment.

[BibT_eX]

[DOI]

Proceedings of the 10th Latin American Test Workshop, 2009

Built-in aging monitoring for safety-critical applications.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Data Acquisition Electronics for PET Mammography Imaging.

[BibT_eX]

Pedro Miguel Rodrigues

Proceedings of the BIODEVICES 2009, 2009

On-Detector Electronics of the Clear PEM Scanner.

[BibT_eX]

Proceedings of the BIODEVICES 2009, 2009

2008

Time Management for Low-Power Design of Digital Systems.

[BibT_eX]

[DOI]

J. Low Power Electron., 2008

Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems.

[BibT_eX]

[DOI]

J. Low Power Electron., 2008

Signal Integrity Enhancement in Digital Circuits.

[BibT_eX]

[DOI]

Leonardo Bisch Piccoli

Marcelino Bicho Dos Santos

IEEE Des. Test Comput., 2008

Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Robust solution for synchronous communication among multi clock domains.

[BibT_eX]

[DOI]

João Varela

Carlos Leong

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Enhancing the Tolerance to Power-Supply Instability in Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations.

[BibT_eX]

[DOI]

Marcelino Bicho Dos Santos

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Using Multiple Clock Schemes and Multi-Temperature Test for Dynamic Fault Detection in Digital Systems.

[BibT_eX]

Proceedings of the 7th Latin American Test Workshop, 2006

Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005

Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip.

[BibT_eX]

[DOI]

D. Barros Júnior

J. Electron. Test., 2005

Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System.

[BibT_eX]

[DOI]

Carlos Leong

P. Bento

Pedro Miguel Rodrigues

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004

On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.

[BibT_eX]

[DOI]

J. Electron. Test., 2004

Modeling and Simulation of Time Domain Faults in Digital Systems.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

2003

Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Hardware/software solution for the automation and real-time control of a wine bottling production line.

[BibT_eX]

[DOI]

Proceedings of 9th IEEE International Conference on Emerging Technologies and Factory Automation, 2003

RTL Test Pattern Generation for High Quality Loosely Deterministic BIST.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

On High-Quality, Low Energy BIST Preparation at RT-Level.

[BibT_eX]

Proceedings of the 3rd Latin American Test Workshop, 2002

RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.

[BibT_eX]

[DOI]

Rosa Rodríguez-Montañés

Joan Figueras

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001

RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems.

[BibT_eX]

[DOI]

J. Electron. Test., 2001

Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Towards E-Management as Enabler for Accelerated Change.

[BibT_eX]

Proceedings of the ICEIS 2001, 2001

Embedded tutorial: TRP: integrating embedded test and ATE.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Quality of Electronic Design: From Architectural Level to Test Coverage.

[BibT_eX]

[DOI]

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

MOSYS A Methodology for Automatic Object Identification from System Specification.

[BibT_eX]

[DOI]

Leandro Buss Becker

Proceedings of the 3rd International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2000), 2000

Optimizing Functional distribution in Complex System Design.

[BibT_eX]

Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000

RTL-based functional test generation for high defects coverage in digital SOCs.

[BibT_eX]

[DOI]

Proceedings of the 5th European Test Workshop, 2000

1999

Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures.

[BibT_eX]

[DOI]

J. Electron. Test., 1999

Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

From system level to defect-oriented test: a case study.

[BibT_eX]

[DOI]

Proceedings of the 4th European Test Workshop, 1999

1998

Defect-oriented test quality assessment using fault sampling and simulation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

An OO Based Methodology for Real-Time HW/SW Systems Modeling.

[BibT_eX]

Proceedings of the Distributed and Parallel Embedded Systems, 1998

1997

Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems.

[BibT_eX]

[DOI]

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996

HW/SW specification using OOM techniques.

[BibT_eX]

[DOI]

Mario Calha

Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

Integrated Approach for Circuit and Fault Extraction of VLSI Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995

Test preparation for high coverage of physical defects in CMOS digital ICs.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Test preparation methodology for high coverage of physical defects in CMOS digital ICs.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs.

[BibT_eX]

[DOI]

Mario Calha

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993

Realistic Fault Analysis of CMOS Analog Building Blocks.

[BibT_eX]

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs.

[BibT_eX]

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992

On the design of a highly testable cell library.

[BibT_eX]

[DOI]

M. Saraiva

A. P. Casimiro

Microprocess. Microprogramming, 1992

Physical DFT for High Coverage of Realistic Faults.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

A methodology for testability enhancement at layout level.

[BibT_eX]

[DOI]

Carlos F. Beltrán Almeida

Júlio Gonçalves

J. Electron. Test., 1991

1990

A strategy for testability enhancement at layout level.

[BibT_eX]

[DOI]

Carlos F. Beltrán Almeida