Isaac Bruce

Orcid: 0000-0003-3959-1293

According to our database¹, Isaac Bruce authored at least 16 papers between 2021 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2024

A BIST Approach to Approximate Co-Testing of Embedded Data Converters.

[BibT_eX]

[DOI]

IEEE Des. Test, June, 2024

A Direct Current-to-digital converter (DCDC) for Advanced Current Measurement in System-on-Chip (SOC) Designs.

[BibT_eX]

[DOI]

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Redundancy Based Resistor String DAC with an all Digital Calibration Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Ultra-Small Area, Highly Linear, Modified All Mosfet Digital-to-Analog Converters with Novel Real Time Digital Calibration Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

A 3-Segment Interpolating String DAC with Low-Cost Built-In-Self-Test Capabilities.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

2023

A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing.

[BibT_eX]

[DOI]

J. Electron. Test., February, 2023

Ultra-Small Area, Highly Linear Sub-Radix R-2R Digital-To-Analog Converters with Novel Calibration Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Small Area, High Accuracy Sub-Radix Resistive Current Mode Digital-To-Analog Converter with Novel Calibration Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022

A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing.

[BibT_eX]

[DOI]

J. Electron. Test., December, 2022

The Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite Testing.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2022

Graph Theory Approach for Multi-site ATE Board Parameter Extraction.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2022

Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel Testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021

Systematic Hardware Error Identification and Calibration for Massive Multisite Testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE European Test Symposium, 2021

Massive Multisite Variability-Aware Die Distribution Estimation for Analog/Mixed-Signal Circuits Test Validation.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Isaac Bruce

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