Irune Agirre

Orcid: 0000-0002-9507-8841

According to our database1, Irune Agirre authored at least 25 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Towards a Contract-Based Definition of Update-Compatibility - Modelling Safety Integration Criteria.
Proceedings of the 25th IEEE International Conference on Intelligent Transportation Systems, 2023

Software Updates Monitoring & Anomaly Detection.
Proceedings of the 8th International Conference on Internet of Things, 2023

UP2DATE software updating framework compliance with safety and security regulations and standards.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023


2022
Safety and security collaborative analysis framework for high-performance embedded computing devices.
Microprocess. Microsystems, September, 2022

A Methodology for Selective Protection of Matrix Multiplications: A Diagnostic Coverage and Performance Trade-off for CNNs Executed on GPUs.
Proceedings of the 6th International Conference on System Reliability and Safety, 2022

2021
Safe and secure software updates on high-performance mixed-criticality systems: The UP2DATE approach.
Microprocess. Microsystems, November, 2021

Towards functional safety compliance of matrix-matrix multiplication for machine learning-based autonomous systems.
J. Syst. Archit., 2021

Multi-core Devices for Safety-critical Systems: A Survey.
ACM Comput. Surv., 2021

Safety and Security Concept for Software Updates on Mixed-criticality Systems.
Proceedings of the 5th International Conference on System Reliability and Safety, 2021

The UP2DATE Baseline Research Platforms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Safe and secure software updates on high-performance embedded systems.
Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2020

UP2DATE: Safe and secure over-the-air software updates on high-performance mixed-criticality systems.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2018
Development and certification of mixed-criticality embedded systems based on probabilistic timing analysis.
PhD thesis, 2018

Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262.
IEEE Trans. Reliab., 2018

2017
On the tailoring of CAST-32A certification guidance to real COTS multicore architectures.
Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application.
Proceedings of the 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, 2017

Software Time Reliability in the Presence of Cache Memories.
Proceedings of the Reliable Software Technologies - Ada-Europe 2017, 2017

2016
Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis.
Proceedings of the 16th International Workshop on Worst-Case Execution Time Analysis, 2016

Automotive Safety Concept Definition for Mixed-Criticality Integration on a COTS Multicore.
Proceedings of the Computer Safety, Reliability, and Security, 2016


2015
Temporal independence validation of an IEC-61508 compliant mixed-criticality system based on multicore partitioning.
Proceedings of the 2015 Forum on Specification and Design Languages, 2015

A Modular Safety Case for an IEC-61508 Compliant Generic Hypervisor.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

A Safety Concept for a Railway Mixed-Criticality Embedded System Based on Multicore Partitioning.
Proceedings of the 15th IEEE International Conference on Computer and Information Technology, 2015


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