Iris Hui-Ru Jiang

Proceedings of the 2024 International Symposium on Physical Design, 2024

Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization.

[BibT_eX]

[DOI]

Chung-Ching Peng

Mohd Mawardi Mohd Razha

Alessandro Uber

Proceedings of the 2024 International Symposium on Physical Design, 2024

Slack Redistributed Register Clustering with Mixed-Driving Strength Multi-bit Flip-Flops.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

2023

Introduction to the Special Section on Advances in Physical Design Automation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., September, 2023

EDA for Domain Specific Computing: An Introduction for the Panel.

[BibT_eX]

[DOI]

David G. Chinnery

Proceedings of the 2023 International Symposium on Physical Design, 2023

Lightning Talk: All Routes to Timing Closure.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Deadlock Resolution for Intelligent Intersection Management with Changeable Trajectories.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE Intelligent Vehicles Symposium, 2022

Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines.

[BibT_eX]

[DOI]

Chih-Wen Yang

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

Intelligent Design Automation for Heterogeneous Integration.

[BibT_eX]

[DOI]

Jiun-Lang Huang

Charlie Chung-Ping Chen

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

Sub-Resolution Assist Feature Generation with Reinforcement Learning and Transfer Learning.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Deadlock Analysis and Prevention for Intersection Management Based on Colored Timed Petri Nets.

[BibT_eX]

[DOI]

Tsung-Lin Tsou

Chung-Wei Lin

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Many-Layer Hotspot Detection by Layer-Attentioned Visual Question Answering.

[BibT_eX]

[DOI]

Yen-Shuo Chen

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Timing macro modeling with graph neural networks.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Novel Guiding Template and Mask Assignment for DSA-MP Hybrid Lithography Using Multiple BCP Materials.

[BibT_eX]

[DOI]

Yi-Ting Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

OpenMPL: An Open-Source Layout Decomposer.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Efficient Mandatory Lane Changing of Connected and Autonomous Vehicles.

[BibT_eX]

[DOI]

Proceedings of the 94th IEEE Vehicular Technology Conference, 2021

Opportunities for 2.5/3D Heterogeneous SoC Integration.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Subresolution Assist Feature Insertion by Variational Adversarial Active Learning and Clustering with Data Point Retrieval.

[BibT_eX]

[DOI]

Sean Shang-En Tseng

James P. Shiely

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

iClaire: A Fast and General Layout Pattern Classification Algorithm With Clip Shifting and Centroid Recreation.

[BibT_eX]

[DOI]

Wei-Chun Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Dynamic Programming Approach to Optimal Lane Merging of Connected and Autonomous Vehicles.

[BibT_eX]

[DOI]

Proceedings of the IEEE Intelligent Vehicles Symposium, 2020

Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Late Breaking Results: Design Dependent Mega Cell Methodology for Area and Power Optimization.

[BibT_eX]

[DOI]

Chih-Wen Yang

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Routing Topology and Time-Division Multiplexing Co-Optimization for Multi-FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Fast and Accurate Wire Timing Estimation on Tree and Non-Tree Net Structures.

[BibT_eX]

[DOI]

Hsien-Han Cheng

Oscar Ou

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Graph-Based Modeling, Scheduling, and Verification for Intersection Management of Intelligent Vehicles.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2019

Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Symposium on Physical Design, 2019

Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Symposium on Physical Design, 2019

DATC RDF-2019: Towards a Complete Academic Reference Design Flow.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

OpenMPL: An Open Source Layout Decomposer: Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

iTimerM: A Compact and Accurate Timing Macro Model for Efficient Hierarchical Timing Analysis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

DATC RDF: An Open Design Flow from Logic Synthesis to Detailed Routing.

[BibT_eX]

[DOI]

CoRR, 2018

OpenMPL: An Open Source Layout Decomposer.

[BibT_eX]

[DOI]

CoRR, 2018

Timing Macro Modeling for Efficient Hierarchical Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Recent Research and Challenges in Multiple Patterning Layout Decomposition.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

DATC RDF: an academic flow from logic synthesis to detailed routing.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

COSAT: congestion, obstacle, and slew aware tree construction for multiple power domain design.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

FastPass: Fast timing path search for generalized timing exception handling.

[BibT_eX]

[DOI]

Tung-Chieh Chen

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Multiple Patterning Layout Decomposition Considering Complex Coloring Rules and Density Balancing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

iTimerM: Compact and Accurate Timing Macro Modeling for Efficient Hierarchical Timing Analysis.

[BibT_eX]

[DOI]

Ting-You Yang

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

DATC RDF: Robust design flow database: Invited paper.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Fast low power rule checking for multiple power domain design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

iClaire: A Fast and General Layout Pattern Classification Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Analytical Clustering Score with Application to Postplacement Register Clustering.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

OWARU: free space-aware timing-driven incremental placement.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

OpenDesign flow database: the infrastructure for VLSI design and design automation research.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Resource-aware functional ECO patch generation.

[BibT_eX]

[DOI]

An-Che Cheng

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Multiple patterning layout decomposition considering complex coloring rules.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Feature detection for image analytics via FPGA acceleration.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2015

Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging.

[BibT_eX]

[DOI]

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

GasStation: Power and Area Efficient Buffering for Multiple Power Domain Design.

[BibT_eX]

[DOI]

Chin-Hsiung Hsu

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

iTimerC 2.0: Fast Incremental Timing and CPPR Analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Criticality-dependency-aware timing characterization and analysis.

[BibT_eX]

[DOI]

King Ho Tam

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2014

PushPull: Short-Path Padding for Timing Error Resilient Circuits.

[BibT_eX]

[DOI]

Sung-Ting Ho

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

DRC-based hotspot detection considering edge tolerance and incomplete specification.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

iTimerC: common path pessimism removal using effective reduction methods.

[BibT_eX]

[DOI]

Yu-Wei Chang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

The overview of 2014 CAD contest at ICCAD.

[BibT_eX]

[DOI]

Natarajan Viswanathan

Tai-Chen Chen

Jin-Fu Li

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Functional ECO Using Metal-Configurable Gate-Array Spare Cells.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

ECO Optimization Using Metal-Configurable Gate-Array Spare Cells.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

FF-bond: multi-bit flip-flop bonding at placement.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

The overview of 2013 CAD contest at ICCAD.

[BibT_eX]

[DOI]

Zhuo Li

Hwei-Tseng Wang

Natarajan Viswanathan

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012

WiT: Optimal Wiring Topology for Electromigration Avoidance.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

ECOS: Stable Matching Based Metal-Only ECO Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Reliability-Driven Power/Ground Routing for Analog ICs.

[BibT_eX]

[DOI]

Jing-Wei Lin

Tsung-Yi Ho

ACM Trans. Design Autom. Electr. Syst., 2012

INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Generic Integer Linear Programming Formulation for 3D IC Partitioning.

[BibT_eX]

[DOI]

Wan-Yu Lee

Tsung-Wan Mei

J. Inf. Sci. Eng., 2012

Novel pulsed-latch replacement based on time borrowing and spiral clustering.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2012

Opening: Introduction to CAD contest at ICCAD 2012: CAD contest.

[BibT_eX]

[DOI]

Zhuo Li

Yih-Lang Li

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Accurate process-hotspot detection using critical design rule extraction.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Timing ECO optimization using metal-configurable gate-array spare cells.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

3DICE: 3D IC cost evaluation based on fast tier number estimation.

[BibT_eX]

[DOI]

Cheng-Chi Chan

Yen-Ting Yu

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Physical Design, 2011

Simultaneous functional and timing ECO.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

Simultaneous voltage island generation and floorplanning.

[BibT_eX]

[DOI]

Houng-Yi Li

Hung-Ming Chen

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Analog placement and global routing considering wiring symmetry.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Physical Design, 2010

Live Demo: ECOS 1.0: A metal-only ECO synthesizer.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Generic integer linear programming formulation for 3D IC partitioning.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

POSA: Power-state-aware Buffered Tree Construction.

[BibT_eX]

[DOI]

Ming-Hua Wu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power.

[BibT_eX]

[DOI]

Wan-Yu Lee

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Matching-based minimum-cost spare cell selection for design changes.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Unification of obstacle-avoiding rectilinear Steiner tree construction.

[BibT_eX]

[DOI]

Shung-Wei Lin

Yen-Ting Yu

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Configurable rectilinear Steiner tree construction for SoC and nano technologies.

[BibT_eX]

[DOI]

Yen-Ting Yu

Proceedings of the 26th International Conference on Computer Design, 2008

Power-state-aware buffered tree construction.

[BibT_eX]

[DOI]

Ming-Hua Wu

Proceedings of the 26th International Conference on Computer Design, 2008

2006

Reliable crosstalk-driven interconnect optimization.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

2004

Simultaneous floor plan and buffer-block optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003

Simultaneous floorplanning and buffer block planning.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning.

[BibT_eX]

[DOI]

Nicholas Chia-Yuan Chang

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2001

On placement and routing of wafer scale memory.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Optimal reliable crosstalk-driven interconnect optimization.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Physical Design, 2000

1999

Optimum loading dispersion for high-speed tree-type decision circuitry.

[BibT_eX]

[DOI]

Jie-Hong Roland Jiang

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

A clustering- and probability-based approach for time-multiplexed FPGA partitioning.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Hierarchical Floorplan Design on the Internet.

[BibT_eX]

[DOI]

Jiann-Horng Lin