Ireneusz Mrozek

According to our database, Ireneusz Mrozek authored at least 16 papers between 2005 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Universal Address Sequence Generator for Memory Built-in Self-test.

Ireneusz Mrozek, Nikolai A. Shevchenko, Vyacheslav N. Yarmolik

Fundam. Informaticae, 2022

2021

Transparent Memory Tests Based on the Double Address Sequences.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Entropy, 2021

2018

Pseudo-Exhaustive Random Access Memory Testing Based on March Tests with Random Background Variation.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

2017

Two-Run RAM March Testing with Address Decimation.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

J. Circuits Syst. Comput., 2017

Optimal Controlled Random Tests.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Proceedings of the Computer Information Systems and Industrial Management, 2017

2016

Multiple Controlled Random Testing.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Fundam. Informaticae, 2016

Methods of Synthesis of Controlled Random Tests.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Proceedings of the Computer Information Systems and Industrial Management, 2016

2015

Controlled method of random test synthesis.

Vyacheslav N. Yarmolik, Ireneusz Mrozek, Svetlana V. Yarmolik

Autom. Control. Comput. Sci., 2015

2013

Analyses of two run march tests with address decimation for BIST procedure.

Ireneusz Mrozek, Svetlana V. Yarmolik

Proceedings of the East-West Design & Test Symposium, 2013

2012

Antirandom Test Vectors for BIST in Hardware/Software Systems.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Fundam. Informaticae, 2012

Iterative Antirandom Testing.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

J. Electron. Test., 2012

2010

Analysis of multibackground memory testing techniques.

Ireneusz Mrozek

Int. J. Appl. Math. Comput. Sci., 2010

2008

Optimal Backgrounds Selection for Multi Run Memory Testing.

Ireneusz Mrozek, Vyacheslav N. Yarmolik

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Multi Background Memory Testing.

Ireneusz Mrozek, Vyacheslav N. Yarmolik, Eugenia Buslowska

Proceedings of the 7th International Conference on Computer Information Systems and Industrial Management Applications, 2008

2007

Address Sequences Generation for Multiple Run Memory Testing.

S. V. Yarmolik, Ireneusz Mrozek, Bartosz Sokol

Proceedings of the 6th International Conference on Computer Information Systems and Industrial Management Applications, 2007

2005

Impact of the address changing on the detection of pattern sensitive faults.

Bartosz Sokol, Ireneusz Mrozek, Wiaczeslaw Yarmolik

Proceedings of the Information Processing and Security Systems., 2005