Ireneusz Brzozowski

According to our database, Ireneusz Brzozowski authored at least 15 papers between 1999 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder.

Ireneusz Brzozowski

ACM Trans. Design Autom. Electr. Syst., May, 2024

2021

Multi-state MRAM cells for hardware neuromorphic computing.

Piotr Rzeszut, Jakub Checinski, Ireneusz Brzozowski, Slawomir Zietek, Witold Skowronski, Tomasz Stobiecki

CoRR, 2021

Software Tool Aiding Analysis and Design of Low-Power Parallel Prefix Adders.

Ireneusz Brzozowski

Proceedings of the 2021 28th International Conference on Mixed Design of Integrated Circuits and System, 2021

2020

Comparative Analysis of Power Consumption of Parallel Prefix Adders.

Ireneusz Brzozowski

Proceedings of the 27th International Conference on Mixed Design of Integrated Circuits and System, 2020

2016

Extraction of temperature dependent parameters for an electrothermal model of thermoelectric energy harvester.

Piotr Dziurdzia, Piotr Bratek, Ireneusz Brzozowski, Wojciech Gelmuda, Jacek Ostrowski, Andrzej Kos

Proceedings of the 2016 MIXDES, 2016

2014

Designing of low-power data oriented adders.

Ireneusz Brzozowski, Andrzej Kos

Microelectron. J., 2014

Double edge class BD hybrid DPWM implementation using linearized LBDD algorithm.

Jacek Jasielski, Stanislaw W. Kuta, Witold Machowski, Ireneusz Brzozowski, Wojciech Kolodziejski

Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

2013

Universal design method of n-to-2n decoders.

Ireneusz Brzozowski, Lukasz Zachara, Andrzej Kos

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

An analysis of full adder cells for low-power data oriented adders design.

Ireneusz Brzozowski, Damian Palys, Andrzej Kos

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

2008

A new approach to power estimation and reduction in CMOS digital circuits.

Ireneusz Brzozowski, Andrzej Kos

Integr., 2008

2007

Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation.

Ireneusz Brzozowski, Andrzej Kos

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2005

Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes.

Ireneusz Brzozowski, Andrzej Kos

Proceedings of the Integrated Circuit and System Design, 2005

2001

Practical Aspects of Logic Synthesis Based on Functional Decomposition.

Mariusz Rawski, Rafal Rzechowski, Zbigniew Jachna, Ireneusz Brzozowski

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

2000

Energy consumption minimisation with new synthesis method.

Ireneusz Brzozowski, Andrzej Kos

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999

Minimization of Power Consumption in Digital Integrated Circuits by Reduction of Switching Activity.

Ireneusz Brzozowski, Andrzej Kos

Proceedings of the 25th EUROMICRO '99 Conference, 1999