Ireneusz Brzozowski

Orcid: 0000-0002-1593-4047

According to our database1, Ireneusz Brzozowski authored at least 15 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder.
ACM Trans. Design Autom. Electr. Syst., May, 2024

2021
Multi-state MRAM cells for hardware neuromorphic computing.
CoRR, 2021

Software Tool Aiding Analysis and Design of Low-Power Parallel Prefix Adders.
Proceedings of the 2021 28th International Conference on Mixed Design of Integrated Circuits and System, 2021

2020
Comparative Analysis of Power Consumption of Parallel Prefix Adders.
Proceedings of the 27th International Conference on Mixed Design of Integrated Circuits and System, 2020

2016
Extraction of temperature dependent parameters for an electrothermal model of thermoelectric energy harvester.
Proceedings of the 2016 MIXDES, 2016

2014
Designing of low-power data oriented adders.
Microelectron. J., 2014

Double edge class BD hybrid DPWM implementation using linearized LBDD algorithm.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

2013
Universal design method of n-to-2n decoders.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

An analysis of full adder cells for low-power data oriented adders design.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

2008
A new approach to power estimation and reduction in CMOS digital circuits.
Integr., 2008

2007
Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2005
Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes.
Proceedings of the Integrated Circuit and System Design, 2005

2001
Practical Aspects of Logic Synthesis Based on Functional Decomposition.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

2000
Energy consumption minimisation with new synthesis method.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999
Minimization of Power Consumption in Digital Integrated Circuits by Reduction of Switching Activity.
Proceedings of the 25th EUROMICRO '99 Conference, 1999


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