Ioannis Tsounis

According to our database, Ioannis Tsounis authored at least 5 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

An Effective TMR Approach for Low-Latency Configurable-Accuracy Adders.

Ioannis Tsounis, Dimitris Agiakatsikas, Mihalis Psarakis

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

2023

A Methodology for Fault-tolerant Pareto-optimal Approximate Designs of FPGA-based Accelerators.

Ioannis Tsounis, Dimitris Agiakatsikas, Mihalis Psarakis

ACM Trans. Embed. Comput. Syst., July, 2023

Detecting Hardware Faults in Approximate Adders via Minimum Redundancy.

Ioannis Tsounis, Dimitris Agiakatsikas, Mihalis Psarakis

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

2021

Analyzing the Impact of Approximate Adders on the Reliability of FPGA Accelerators.

Ioannis Tsounis, Athanasios Papadimitriou, Mihalis Psarakis

Proceedings of the 26th IEEE European Test Symposium, 2021

2019

Analyzing the Resilience to SEUs of an Image Data Compression Core in a COTS SRAM FPGA.

Ioannis Tsounis, Antonis Tsigkanos, Vasileios Vlagkoulis, Mihalis Psarakis, Nektarios Kranitis, Antonis M. Paschalis

Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2019