Ioannis Tsiokanos

According to our database, Ioannis Tsiokanos authored at least 11 papers between 2018 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

ARETE: Accurate Error Assessment via Machine Learning-Guided Dynamic-Timing Analysis.

Ioannis Tsiokanos, Styliani Tompazi, Giorgis Georgakoudis, Lev Mukhanov, Georgios Karakonstantis

IEEE Trans. Computers, April, 2023

Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning.

Styliani Tompazi, Ioannis Tsiokanos, Jesús Martínez del Rincón, Georgios Karakonstantis

IEEE Des. Test, February, 2023

2022

Instruction-aware Learning-based Timing Error Models through Significance-driven Approximations.

Styliani Tompazi, Ioannis Tsiokanos, Jesús Martínez del Rincón, Lev Mukhanov, Georgios Karakonstantis

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021

ExHero: Execution History-Aware Error-Rate Estimation in Pipelined Designs.

Ioannis Tsiokanos, Georgios Karakonstantis

IEEE Micro, 2021

DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices.

Ioannis Tsiokanos, Jack Miskelly, Chongyan Gu, Máire O'Neill, Georgios Karakonstantis

ACM J. Emerg. Technol. Comput. Syst., 2021

Boosting Microprocessor Efficiency: Circuit- and Workload-Aware Assessment of Timing Errors.

Ioannis Tsiokanos, George Papadimitriou, Dimitris Gizopoulos, Georgios Karakonstantis

Proceedings of the IEEE International Symposium on Workload Characterization, 2021

2020

Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation.

Dimitrios Garyfallou, Ioannis Tsiokanos, Nestor E. Evmorfopoulos, Georgios I. Stamoulis, Georgios Karakonstantis

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search.

Ioannis Tsiokanos, Lev Mukhanov, Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, Georgios Karakonstantis

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation.

Ioannis Tsiokanos, Lev Mukhanov, Georgios Karakonstantis

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment: Case Study on a Floating-Point Unit.

Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Minimization of Timing Failures in Pipelined Designs via Path Shaping and Operand Truncation.

Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018