Ioannis Tsatsaragkos

Orcid: 0000-0001-8297-7277

According to our database1, Ioannis Tsatsaragkos authored at least 10 papers between 2011 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2018
A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2015
Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

2012
Error Floor Compensation for LDPC Codes Using Concatenated Schemes.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Propagation of LLR Saturation and Quantization Error in LDPC Min-Sum Iterative Decoding.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A flexible layered LDPC decoder.
Proceedings of the 8th International Symposium on Wireless Communication Systems, 2011

Digital baseband challenges for a 60GHz gigabit link.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Multiple LDPC decoder of very low bit-error rate.
Proceedings of the 17th International Conference on Digital Signal Processing, 2011

A syndrome-based LDPC decoder with very low error floor.
Proceedings of the 17th International Conference on Digital Signal Processing, 2011


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