Ioannis Seitanidis
Orcid: 0000-0002-9693-0135
According to our database1,
Ioannis Seitanidis
authored at least 12 papers
between 2014 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
2017
Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Computers, 2016
Powermax: an automated methodology for generating peak-power traffic in networks-on-chip.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014