Ioannis Savidis

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

EDA-ML: Graph Representation Learning Framework for Digital IC Design Automation.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Edge-weighted Graph Neural Networks for Post-placement Interconnect Capacitance Estimation of Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

DNA: DC Nodal Analysis Attack for Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Block Configuration Algorithms for a Reconfigurable Analog Array.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

EDA-schema: A Graph Datamodel Schema and Open Dataset for Digital Design Automation.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Harnessing Heterogeneity for Targeted Attacks on 3-D ICs.

[BibT_eX]

[DOI]

Alec Aversa

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023

Hidden Costs of Analog Deobfuscation Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

Hybrid Utilization of Subgraph Isomorphism and Relational Graph Convolutional Networks for Analog Functional Grouping Annotation.

[BibT_eX]

[DOI]

Isabel Song

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Power Side-Channel Attack on Flash ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

Transfer of Performance Models Across Analog Circuit Topologies with Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Graph Representation Learning for Gate Arrival Time Prediction.

[BibT_eX]

[DOI]

Saran Phatharodom

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits.

[BibT_eX]

[DOI]

Avesta Sasan

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Adaptive-Gravity: A Defense Against Adversarial Samples.

[BibT_eX]

[DOI]

Ali Mirzaeian

Zhi Tian

Sai Manoj P. D.

Banafsheh S. Latibari

Avesta Sasan

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Transfer Learning for Reuse of Analog Circuit Sizing Models Across Technology Nodes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Synthesis of Coupling Capacitance Based Hidden State Transitions for Sequential Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Reconfigurable Analog Array for Hardware Security.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Practical Performance of Analog Attack Techniques.

[BibT_eX]

[DOI]

Sayed Aresh Beheshti-Shirazi

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis.

[BibT_eX]

[DOI]

Tanmoy Chowdhury

Ashkan Vakil

Banafsheh Saber Latibari

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021

Performance and Security Analysis of Parameter-Obfuscated Analog Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Synthesis of Hidden State Transitions for Sequential Logic Locking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN Accelerators.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Variation-aware Analog Circuit Sizing with Classifier Chains.

[BibT_eX]

[DOI]

Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021

Reconfigurable Array for Analog Applications.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

SAT-attack Resilience Measure for Access Restricted Circuits.

[BibT_eX]

[DOI]

Saran Phatharodom

Avesta Sasan

Sayed Aresh Beheshti-Shirazi

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Energy Efficient Computing with Heterogeneous DNN Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing.

[BibT_eX]

[DOI]

Microelectron. J., 2020

Recycling of unused leakage current for energy efficient multi-voltage systems.

[BibT_eX]

[DOI]

Microelectron. J., 2020

Physical Layer Encryption for Wireless OFDM Communication Systems.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2020

CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing.

[BibT_eX]

[DOI]

Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

Dynamic idle core management and leakage current reuse in MPSoC platforms.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Security Vulnerabilities of Obfuscated Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Modeling SAT-Attack Search Complexity.

[BibT_eX]

[DOI]

Saran Phatharodom

Nagarajan Kandasamy

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Reducing Logic Locking Key Leakage through the Scan Chain.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.

[BibT_eX]

[DOI]

Ibrahim Abe M. Elfadel

Mehran Mozaffari Kermani

IEEE Trans. Very Large Scale Integr. Syst., 2019

Securing Wireless Communication via Hardware-Based Packet Obfuscation.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2019

Robust Low Power Clock Synchronization for Multi-Die Systems.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Mesh Based Obfuscation of Analog Circuit Properties.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Increasing the SAT Attack Resiliency of In-Cone Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Reusing Leakage Current for Improved Energy Efficiency of Multi-Voltage Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Applying Swarm Intelligence to Distributed On-Chip Power Management.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018

ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Time Domain Sequential Locking for Increased Security.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Noise Constrained Optimum Selection of Supply Voltage for IoT Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Securing the Systems of the Future - Techniques for a Shifting Attack Space.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Clock tree synthesis for heterogeneous 3-D integrated circuits.

[BibT_eX]

[DOI]

Isuru Daulagala

Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

Bi-directional input/output circuits with integrated level shifters for near-threshold computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Protecting analog circuits with parameter biasing obfuscation.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Physical gate based preamble obfuscation for securing wireless communication.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Computing, 2017

Parameter biasing obfuscation for analog IP protection.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

Heterogeneous 3-D circuits: Integrating free-space optics with CMOS.

[BibT_eX]

[DOI]

Microelectron. J., 2016

A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures.

[BibT_eX]

[DOI]

Kostas Siozios

Dimitrios Soudris

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Energy efficient on-chip power delivery with run-time voltage regulator clustering.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Reducing logic encryption overhead through gate level key insertion.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Robust near-threshold inverter with improved performance for ultra-low power applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Load Balanced On-Chip Power Delivery for Average Current Demand.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Reduced Overhead Gate Level Logic Encryption.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits.

[BibT_eX]

[DOI]

Boris Vaisband

IEEE Trans. Very Large Scale Integr. Syst., 2015

Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping.

[BibT_eX]

[DOI]

Maria Malik

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Run-time voltage detection circuit for 3-D IC power delivery.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Thermal conduction path analysis in 3-D ICs.

[BibT_eX]

[DOI]

Boris Vaisband

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Power Noise in TSV-Based 3-D Integrated Circuits.

[BibT_eX]

[DOI]

Selçuk Köse

IEEE J. Solid State Circuits, 2013

2011

Clock Distribution Networks in 3-D Integrated Systems.

[BibT_eX]

[DOI]

Vasilis F. Pavlidis

IEEE Trans. Very Large Scale Integr. Syst., 2011

Thermal analysis of oxide-confined VCSEL arrays.

[BibT_eX]

[DOI]

Jinhui Wang

Microelectron. J., 2011

Clock distribution models of 3-D integrated systems.

[BibT_eX]

[DOI]

Vasilis F. Pavlidis

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits.

[BibT_eX]

[DOI]

Microelectron. J., 2010

An intra-chip free-space optical interconnect.

[BibT_eX]

[DOI]

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2008

Electrical modeling and characterization of 3-D vias.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Clock distribution networks for 3-D ictegrated Circuits.

[BibT_eX]

[DOI]

Vasilis F. Pavlidis