Ioannis L. Syllaios

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Hybrid-DPLL-based constant-envelope modulator for Internet-of-Things chipsets.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015

DPLL with hybrid ΔΣ phase/frequency detector.

[BibT_eX]

[DOI]

Henrik T. Jensen

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2012

Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011

Multi-clock domain analysis and modeling of all-digital frequency synthesizers.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Recombination of Envelope and Phase Paths in Wideband Polar Transmitters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2008

Time-Domain Modeling of an RF All-Digital PLL.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

2007

On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios.

[BibT_eX]

[DOI]

Proceedings of the IEEE 18th International Symposium on Personal, 2007

Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

A generalized signal reconstruction method for designing interpolation filters.

[BibT_eX]

[DOI]