Ioannis A. Papistas
Orcid: 0000-0002-1771-7011
According to our database1,
Ioannis A. Papistas
authored at least 17 papers
between 2015 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
-
on dl.acm.org
On csauthors.net:
Bibliography
2024
11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE J. Solid State Circuits, 2023
2022
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration.
ACM Trans. Design Autom. Electr. Syst., 2022
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm<sup>2</sup> in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
CoRR, 2019
2018
Efficient Modeling of Crosstalk Noise on Power Distribution Networks for Contactless 3-D ICs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Inter-Tier Crosstalk Noise On Power Delivery Networks For 3-D ICs With Inductively-Coupled Interconnects.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
2015
Bandwidth-to-area comparison of through silicon vias and inductive links for 3-D ICs.
Proceedings of the European Conference on Circuit Theory and Design, 2015