Insup Shin

According to our database1, Insup Shin authored at least 15 papers between 2009 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2016
One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014
HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Accurate gate delay Extraction for Timing Analysis of Body-Biased Circuits.
J. Circuits Syst. Comput., 2013

A pipeline architecture with 1-cycle timing error correction for low voltage operations.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Synthesis of Active-Mode Power-Gating Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Gate delay modeling for static timing analysis of body-biased circuits.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Introducing irregularity to routing architecture of structured ASIC for better routability.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011
Selectively patterned masks: Structured ASIC with asymptotically ASIC performance.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Synthesis and implementation of active mode power gating circuits.
Proceedings of the 47th Design Automation Conference, 2010

2009
HLS-l: High-level synthesis of high performance latch-based circuits.
Proceedings of the Design, Automation and Test in Europe, 2009

Register allocation for high-level synthesis using dual supply voltages.
Proceedings of the 46th Design Automation Conference, 2009


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